Chi S Chang

US Patent:

6346467, Feb 12, 2002

Filed:

Aug 28, 2000

Appl. No.:

09/649027

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Nagoya, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kanagawa

International Classification:

H01L 213205

US Classification:

438594, 438264, 438595

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell by silicon nitride capping and sidewall layers. The inventive methodology advantageously prevents deleterious oxidation during subsequent processing at high temperature and in an oxidizing ambient.

US Patent:

6356482, Mar 12, 2002

Filed:

Sep 7, 2000

Appl. No.:

09/657029

Inventors:

Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518503, 36518518

Abstract:

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure having charge stored near both the source and drain. During the erase operation, a negative gate erase voltage is applied along with a positive source and drain voltage to improve the speed of erase operations and performance of the non-volatile memory cell after many program-erase cycles.

US Patent:

6381179, Apr 30, 2002

Filed:

Sep 7, 2000

Appl. No.:

09/656675

Inventors:

Narbeh Derhacobian - Belmont CA
Michael Van Buskirk - Saratoga CA
Chi Chang - Redwood City CA
Daniel Sobek - Portola Valley CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G11C 1604

US Classification:

36518529, 36518528

Abstract:

An erase operation is performed on a non-volatile memory cell with an oxide-nitride-oxide structure by using an initial negative gate erase voltage to improve the speed and performance of the non-volatile memory cell after many program-erase cycles. By utilizing a negative gate erase voltage, the cell does not require increased erase time to reduce the cell threshold and avoid incomplete erase conditions as the number of program-erase cycles increases.

US Patent:

6399984, Jun 4, 2002

Filed:

Jun 15, 2001

Appl. No.:

09/882242

Inventors:

Yider Wu - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Yu Sun - Saratoga CA
Tuan Duc Pham - Santa Clara CA
Jean Y. Yang - Palo Alto CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257316, 257314

Abstract:

A predetermined species such as nitrogen is placed at an interface between a bit line junction and a dielectric layer of a control dielectric structure of a flash memory device to minimize degradation of such an interface by minimizing formation of interface defects during program or erase operations of the flash memory device. The predetermined species such as nitrogen is implanted into a bit line junction of the flash memory device. A thermal process is performed that heats up the semiconductor wafer such that the predetermined species such as nitrogen implanted within the semiconductor wafer thermally drifts to the interface between the bit line junction and the control dielectric structure during the thermal process. The predetermined species such as nitrogen at the interface minimizes formation of interface defects and thus degradation of the interface with time during the program or erase operations of the flash memory device.

US Patent:

6420752, Jul 16, 2002

Filed:

Feb 11, 2000

Appl. No.:

09/502163

Inventors:

Minh Van Ngo - Fremont CA
Yu Sun - Saratoga CA
Fei Wang - San Jose CA
Mark T. Ramsbey - Sunnyvale CA
Chi Chang - Redwood City CA
Angela T. Hui - Fremont CA
Mark S. Chang - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29788

US Classification:

257315, 257314, 36518501, 36518526

Abstract:

A semiconductor device for minimizing auto-doping problems is disclosed. An etch stop layer is eliminated and is replaced with a consumable liner oxide layer so that stacked gate structures of the device can be positioned closer together, thus permitting shrinking of the device. The liner oxide layer is formed directly over a substrate and in contact with stacked gate structures, sidewall spacers, and sources and drains formed on the substrate, and serves as an auto-doping barrier for the dielectric layer to prevent boron and phosphorous formed in the dielectric layer from auto-doping into the sources and drains.

US Patent:

6429108, Aug 6, 2002

Filed:

Aug 31, 2000

Appl. No.:

09/652136

Inventors:

Chi Chang - Redwood City CA
Richard J. Huang - Cupertino CA
Keizaburo Yoshie - Tokyo, JP
Yu Sun - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited - Kawasaki

International Classification:

H01L 213205

US Classification:

438587

Abstract:

A tungsten gate MOS transistor and a memory cell useful in flash EEPROM devices are fabricated by encapsulating the tungsten gate electrode contact of each of the MOS transistor and floating gate memory cell with silicon nitride capping and sidewall layers, thereby preventing deleterious oxidation during subsequent processing at high temperature in an oxidizing ambient.

US Patent:

6444530, Sep 3, 2002

Filed:

May 25, 1999

Appl. No.:

09/318429

Inventors:

Hung-Sheng Chen - San Jose CA
Unsoon Kim - San Clara CA
Yu Sun - Saratoga CA
Chi Chang - Redwood City CA
Mark Ramsbey - Sunnyvale CA
Mark Randolph - San Jose CA
Tatsuya Kajita - Cupertino CA
Angela Hui - Fremont CA
Fei Wang - San Jose CA
Mark Chang - Los Altos CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21336

US Classification:

438303, 428622, 428629, 428634, 428656

Abstract:

A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.

US Patent:

6444539, Sep 3, 2002

Filed:

Feb 15, 2001

Appl. No.:

09/784892

Inventors:

Yu Sun - Saratoga CA
Angela T. Hui - Fremont CA
Tatsuya Kajita - Aizuwakamatsu, JP
Mark Chang - Los Altos CA
Chi Chang - Redwood City CA
Hung-Sheng Chen - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA
Fujitsu Limited

International Classification:

H01L 2176

US Classification:

438424, 438425, 438426, 438430, 438435, 438437, 438444, 438438, 438446, 438452

Abstract:

A semiconductor apparatus and method for producing shallow trench isolation. The method includes the steps providing a semiconductor substrate member fabricated having a thin barrier oxide layer on which are fabricated a plurality of spaced apart silicon nitride pads. The regions between the spaced apart nitride pads delineate U-shaped regions for forming shallow isolation trenches and are layered with silicon oxide and polysilicon. The U-shaped regions provide a buffer region of oxide and polysilicon material adjacent opposing silicon nitride pads that prevent erosion of the nitride during etch formation of the isolation trench. The polysilicon is further etched to form a wider, second U-shaped region having sloped sidewalls that provide opposing spacer-forming buffer material that facilitates forming a V-shaped isolation trench region into the semiconductor substrate member a predetermined depth without eroding the silicon nitride pads. The V-shaped trench is subsequently filled with silicon dioxide that is grown by a hot thermal oxide process. The upper portion of the V-shaped isolation trench may be further filled with deposited silicon dioxide followed by a chemical mechanical polishing process.