Chen W Wang

Author:

Chen Wang

ISBN #:

3540253696

Author:

Chen Wang

ISBN #:

7505949896

US Patent:

7302624, Nov 27, 2007

Filed:

Aug 25, 2005

Appl. No.:

11/213327

Inventors:

Janusz Rajski - West Linn OR, US
Grzegorz Mrugalski - Wilsonville OR, US
Artur Pogiel - 89-200 Szubin, PL
Jerzy Tyszer - 61-249 Poznam, PL
Chen Wang - Tigard OR, US

International Classification:

G01R 31/28

US Classification:

714732, 714726

Abstract:

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, one or more signatures are received that indicate the presence of one or more errors in one or more corresponding compressed test responses. Scan cells in the circuit-under-test that caused the errors are identified by analyzing the signatures. In this exemplary embodiment, the analysis includes selecting a scan cell candidate that potentially caused an error in a compressed test response based at least partially on a weight value associated with the scan cell candidate, the weight value being indicative of the likelihood that the scan cell candidate caused the error. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

US Patent:

7370254, May 6, 2008

Filed:

Feb 13, 2004

Appl. No.:

10/778950

Inventors:

Janusz Rajski - West Linn OR, US
Jerzy Tyszer - 61-249 Poznan, PL
Chen Wang - Tigard OR, US
Grzegorz Mrugalski - Wilsonville OR, US
Artur Pogiel - 89-200 Szubin, PL

International Classification:

G01R 31/28

US Classification:

714726, 714733, 714732

Abstract:

The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.

US Patent:

7386778, Jun 10, 2008

Filed:

Oct 20, 2005

Appl. No.:

11/255777

Inventors:

Jon Udell - West Linn OR, US
Chen Wang - Tigard OR, US
Mark Kassab - Wilsonville OR, US
Janusz Rajski - West Linn OR, US

International Classification:

G01R 31/28

US Classification:

714738

Abstract:

Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e. g. , parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner.

US Patent:

7437640, Oct 14, 2008

Filed:

Aug 25, 2005

Appl. No.:

11/213672

Inventors:

Janusz Rajski - West Linn OR, US
Grzegorz Mrugalski - Wilsonville OR, US
Artur Pogiel - 89-200 Szubin, PL
Jerzy Tyszer - 61-249 Poznan, PL
Chen Wang - Tigard OR, US

International Classification:

G01R 31/28

US Classification:

714729, 714727

Abstract:

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, a compactor for compacting test responses in a circuit-under-test is disclosed. In this embodiment, the compactor includes an injector network comprising combinational logic and includes injector-network outputs and injector-network inputs. At least some of the injector-network inputs are logically coupled to two or more injector-network outputs according to respective injector polynomials. The exemplary compactor further comprises a selection circuit that includes selection-circuit outputs coupled to the injector-network inputs and selection-circuit inputs coupled to scan-chain outputs of the circuit-under-test. The selection circuit is configured to selectively route signals from the scan-chain outputs to the injector-network inputs according to one of plural different input configurations.

US Patent:

7509550, Mar 24, 2009

Filed:

Aug 25, 2005

Appl. No.:

11/213316

Inventors:

Janusz Rajski - West Linn OR, US
Grzegorz Mrugalski - Wilsonville OR, US
Artur Pogiel - 89-200 Szubin, PL
Jerzy Tyszer - 61-249 Poznan, PL
Chen Wang - Tigard OR, US

International Classification:

G01R 31/3193
G01R 31/40

US Classification:

714732, 714726

Abstract:

Methods, apparatus, and systems for diagnosing failing scan cells from compressed test responses are disclosed herein. For example, in one nonlimiting exemplary embodiment, at least one error signature comprising multiple bits (including one or more error bits) is received. Plural potential-error-bit-explaining scan cell candidates are evaluated using a search tree. A determination is made as to whether one or more of the evaluated scan cell candidates explain the error bits in the error signature and thereby constitute one or more failing scan cells. An output is provided of any such one or more failing scan cells determined. Tangible computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Tangible computer-readable media comprising lists of failing scan cells identified by any of the disclosed methods are also provided.

US Patent:

7509600, Mar 24, 2009

Filed:

Nov 1, 2004

Appl. No.:

10/979496

Inventors:

Janusz Rajski - West Linn OR, US
Huaxing Tang - Wilsonville OR, US
Chen Wang - Tigard OR, US

International Classification:

G06F 17/50

US Classification:

716 4, 715 5

Abstract:

Disclosed below are representative embodiments of methods, apparatus, and systems for generating test patterns having an increased ability to detect untargeted defects. In one exemplary embodiment, for instance, one or more deterministic test values for testing targeted faults (e. g. , stuck-at faults or bridging faults) in an integrated circuit design are determined. Additional test values that increase detectability of one or more untargeted defects during testing are determined. One or more test patterns are created that include at least a portion of the deterministic test values and at least a portion of the additional test values. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or comprising test patterns generated by any of the disclosed embodiments are also disclosed.

US Patent:

7669101, Feb 23, 2010

Filed:

May 8, 2008

Appl. No.:

12/117701

Inventors:

Jon Udell - West Linn OR, US
Chen Wang - Tigard OR, US
Mark Kassab - Wilsonville OR, US
Janusz Rajski - West Linn OR, US

International Classification:

G01R 31/28

US Classification:

714738

Abstract:

Described herein are methods and systems for distributed execution of circuit testing algorithms, or portions thereof. Distributed processing can result in faster processing. Algorithms or portions of algorithms that are independent from each other can be executed in a non-sequential manner (e. g. , parallel) over a network of plurality of processors. The network includes a controlling processor that can allocate tasks to other processors and conduct the execution of some tasks on its own. Dependent algorithms, or portions thereof, can be performed on the controlling processor or one of the controlled processors in a sequential manner. For algorithms that are highly sequential in nature, portions of algorithms can be modified to delay the need for dependent results between algorithm portions by creating a rolling window of independent tasks that is iterated.

US Patent:

7743302, Jun 22, 2010

Filed:

Jan 30, 2008

Appl. No.:

12/012039

Inventors:

Janusz Rajski - West Linn OR, US
Jerzy Tyszer - 61-249 Poznan, PL
Chen Wang - Tigard OR, US
Grzegorz Mrugalski - Wilsonville OR, US
Artur Pogiel - 89-200 Szubin, PL

International Classification:

G01R 31/28

US Classification:

714734, 714732, 714729

Abstract:

The present disclosure describes embodiments of a compactor for compressing test results in an integrated circuit and methods for using and designing such embodiments. The disclosed compactors can be utilized, for example, as part of any scan-based design. Moreover, any of the disclosed compactors can be designed, simulated, and/or verified in a computer-executed application, such as an electronic-design-automation (“EDA”) software tool. Embodiments of a method for diagnosing faults in the disclosed compactor embodiments are also described.