Charles J Tabony from 12012 Carmel Park Ln, Austin, TX 78727, age 43

Us Patents

Dedicated Arithmetic Decoding Instruction
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US Patent:

20110125987, May 26, 2011
Filed:

Nov 20, 2009
Appl. No.:

12/622998
Inventors:

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Mao Zeng - Austin TX, US
Christopher Edward Koob - Round Rock TX, US
Charles Joseph Tabony - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
G06F 9/302
US Classification:

712208, 712221, 712E09016, 712E09017
Abstract:

A dedicated arithmetic decoding instruction is disclosed. In a particular embodiment, an apparatus includes a memory and a processor coupled to the memory. The processor is configured to execute general purpose instructions and to execute a dedicated arithmetic decoding instruction retrieved from the memory.

System And Method Of Processing Hierarchical Very Long Instruction Packets
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US Patent:

20110219212, Sep 8, 2011
Filed:

Mar 3, 2010
Appl. No.:

12/716359
Inventors:

Lucian Codrescu - Austin TX, US
Erich James Plondke - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US
Charles Joseph Tabony - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
US Classification:

712208, 712E09016
Abstract:

A system and method of processing a hierarchical very long instruction word (VLIW) packet is disclosed. In a particular embodiment, a method of processing instructions is disclosed. The method includes receiving a hierarchical VLIW packet of instructions and decoding an instruction from the packet to determine whether the instruction is a single instruction or whether the instruction includes a subpacket that includes a plurality of sub-instructions. The method also includes, in response to determining that the instruction includes the subpacket, executing each of the sub-instructions.

Methods And Apparatus For Constant Extension In A Processor
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US Patent:

20120284488, Nov 8, 2012
Filed:

May 3, 2011
Appl. No.:

13/099425
Inventors:

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Charles Joseph Tabony - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
US Classification:

712205, 712208, 712E09028
Abstract:

Programs often require constants that cannot be encoded in a native instruction format, such as -bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 2-bits for example, and the target instruction provides a second set of constant bits, such as -bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Methods And Apparatus For Constant Extension In A Processor
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US Patent:

20120284489, Nov 8, 2012
Filed:

Jun 8, 2011
Appl. No.:

13/155565
Inventors:

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Charles Joseph Tabony - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
US Classification:

712226, 712E09028
Abstract:

Programs often require constants that cannot be encoded in a native instruction format, such as 32-bits. To provide an extended constant, an instruction packet is formed with constant extender information and a target instruction. The constant extender information encoded as a constant extender instruction provides a first set of constant bits, such as 26-bits for example, and the target instruction provides a second set of constant bits, such as 6-bits. The first set of constant bits are combined with the second set of constant bits to generate an extended constant for execution of the target instruction. The extended constant may be used as an extended source operand, an extended address for memory access instructions, an extended address for branch type of instructions, and the like. Multiple constant extender instructions may be used together to provide larger constants than can be provided by a single extension instruction.

Table Call Instruction For Frequently Called Functions
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US Patent:

20130024663, Jan 24, 2013
Filed:

Jul 19, 2011
Appl. No.:

13/185644
Inventors:

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Charles Joseph Tabony - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US
Evandro Carlos Menezes - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
US Classification:

712208, 712E09028
Abstract:

An apparatus includes a memory that stores an instruction including an opcode and an operand. The operand specifies an immediate value or a register indicator of a register storing the immediate value. The immediate value is usable to identify a function call address. The function call address is selectable from a plurality of function call addresses.

Floating Point Constant Generation Instruction
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US Patent:

20130212357, Aug 15, 2013
Filed:

Feb 9, 2012
Appl. No.:

13/369693
Inventors:

Erich James Plondke - Austin TX, US
Lucian Codrescu - Austin TX, US
Charles Joseph Tabony - Austin TX, US
Swaminathan Balasubramanian - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
G06F 9/302
US Classification:

712208, 712220, 712221, 712E09017, 712E09028
Abstract:

Systems and methods for generating a floating point constant value from an instruction are disclosed. A first field of the instruction is decoded as a sign bit of the floating point constant value. A second field of the instruction is decoded to correspond to an exponent value of the floating point constant value. A third field of the instruction is decoded to correspond to the significand of the floating point constant value. The first field, the second field, and the third field are combined to form the floating point constant value. The exponent value may include a bias, and a bias constant may be added to the exponent value to compensate for the bias. The third field may comprise the most significant bits of the significand. Optionally, the second field and the third field may be shifted by first and second shift values respectively before they are combined to form the floating point constant value.

Bimodal Compare Predictor Encoded In Each Compare Instruction
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US Patent:

20130283023, Oct 24, 2013
Filed:

Apr 18, 2012
Appl. No.:

13/449754
Inventors:

Charles Joseph Tabony - Austin TX, US
Lucian Codrescu - Austin TX, US
Suresh K. Venkumahanti - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
US Classification:

712240, 712E09028
Abstract:

Systems and methods for branch prediction, including predicting evaluation of a producer instruction such as a compare instruction, by encoding a prediction field in the producer instruction, and predicting evaluation of the producer instruction by using the encoded prediction field. A consumer instruction such as a conditional branch instruction predicated on the producer instruction can be speculatively executed based on the predicted evaluation of the producer instruction. The producer instruction is executed in an execution pipeline to determine an actual evaluation of the producer instruction, and the prediction field is updated, if necessary, based on the actual evaluation and the predicted evaluation. The producer instruction can be updated in memory with the updated prediction field.

System And Method Of Selectively Committing A Result Of An Executed Instruction
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US Patent:

20090235051, Sep 17, 2009
Filed:

Mar 11, 2008
Appl. No.:

12/045825
Inventors:

Lucian Codrescu - Austin TX, US
Robert Allan Lester - Round Rock TX, US
Charles Joseph Tabony - Austin TX, US
Erich James Plondke - Austin TX, US
Mao Zeng - Austin TX, US
Suresh Venkumahanti - Austin TX, US
Ajay Anant Ingle - Austin TX, US
Assignee:

QUALCOMM INCORPORATED - San Diego CA
International Classification:

G06F 9/30
G06F 9/312
US Classification:

712205, 712216, 712218, 712E09016, 712E09033
Abstract:

In a particular embodiment, a method is disclosed that includes receiving an instruction packet including a first instruction and a second instruction that is dependent on the first instruction at a processor having a plurality of parallel execution pipelines, including a first execution pipeline and a second execution pipeline. The method further includes executing in parallel at least a portion of the first instruction and at least a portion of the second instruction. The method also includes selectively committing a second result of executing the at least a portion of the second instruction with the second execution pipeline based on a first result related to execution of the first instruction with the first execution pipeline.