Cecilia Te Ozdemir from 123 Old Orchard Ct, Los Gatos, CA 95032, age 57, Phone: 408 356-0439

Variable Latency Interface For Read/Write Channels
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US Patent:

20110314324, Dec 22, 2011
Filed:

Oct 15, 2010
Appl. No.:

12/925253
Inventors:

Cecilia Ozdemir - Los Gatos CA, US
Assignee:

STMicroelectronics, Inc. - Carrollton TX
International Classification:

G06F 13/10
G06F 1/04
US Classification:

713600, 710 58
Abstract:

A variable latency interface and method for managing variable latency. An apparatus includes a storage device controller and a read/write channel coupled to the storage device controller by a variable latency interface. The variable latency interface includes a media control component configured for read and write operations. The variable latency interface also includes a data transfer component configured for read and write operations. A read or write operation in the media control component is offset from a respective read or write operation in the data transfer component by a latency period.

Dual Master Jtag Method, Circuit, And System
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US Patent:

20140298122, Oct 2, 2014
Filed:

Mar 28, 2013
Appl. No.:

13/852223
Inventors:

- Coppell TX, US
ULDERIC LACOUR - San Jose CA, US
CECILIA OZDEMIR - Los Gatos CA, US
Assignee:

STMicroelectronics, Inc. - Coppell TX
International Classification:

G06F 11/25
US Classification:

714724
Abstract:

A dual-master controller includes a plurality of JTAG data registers including a controller-mode register that stores information indicating a standard JTAG or a processor-controlled mode of operation. A JTAG TAP controller receives control signals over a standard test access port and a processor controller receives processor control signals over an external processor bus. A selection multiplexer outputs either signals on the standard JTAG access port or the external processor bus responsive to a JTAG mode selection signal. A logic circuit activates the JTAG mode selection signal responsive to the force JTAG signal being active or information in the controller-mode register indicating the standard JTAG mode, and deactivates the JTAG mode selection signal responsive to the force JTAG signal being deactivated or the information in the controller-mode register indicating the processor-controller mode. An instruction decoder and multiplexer circuit applies control signals from the selection multiplexer to control the JTAG data registers.