Carolyn K Mccormick

US Patent:

6927346, Aug 9, 2005

Filed:

Dec 20, 2002

Appl. No.:

10/326901

Inventors:

Carolyn R. McCormick - Chandler AZ, US
Terrance J. Dishongh - Hillsboro OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K001/16

US Classification:

174260, 174262, 29840, 29843, 2281801, 22818021

Abstract:

Apparatus and methods for interconnecting a SMT component interconnect to a via-in-pad (VIP) interconnect. A first reflowable material is deposited on the VIP bond pad. A sphere having a higher melt temperature than the reflow temperature of the first interconnect material is deposited on the first interconnect material. A first reflow process is performed to interconnect the sphere and the VIP bond pad while the sphere remains solid, and the first reflowable material preventing the first interconnect material from migrating into the via-in-pad.

US Patent:

7352061, Apr 1, 2008

Filed:

May 20, 2005

Appl. No.:

11/134784

Inventors:

Mitul B. Modi - Phoenix AZ, US
Patricia A. Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn R. McCormick - Chandler AZ, US
Sankara J. Subramanian - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/12
H05K 7/00

US Classification:

257700, 257E23077, 257E23007, 257E23194, 257E23008, 257E23069, 257E23173, 257668, 257701, 257758, 257774, 257759, 257703, 257778, 361748, 361760

Abstract:

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as its modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

US Patent:

7633142, Dec 15, 2009

Filed:

Oct 26, 2007

Appl. No.:

11/977980

Inventors:

Mitul B. Modi - Phoenix AZ, US
Patricia A. Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn R. McCormick - Chandler AZ, US
Sankara J. Subramanian - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/12
H05K 7/00

US Classification:

257668, 257E23174, 257E23007, 257E23077, 257E23194, 257E23008, 257E23069, 257E23173, 257701, 257758, 257759, 257703, 257778, 257700, 361760, 361748

Abstract:

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon considerations such as it modulus, its coefficient of thermal expansion, and/or the resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established be considering the reflective density in opposing conductive build-up layers above and below the core region.

US Patent:

8399291, Mar 19, 2013

Filed:

Jun 29, 2005

Appl. No.:

11/169518

Inventors:

Patricia A Brusso - Chandler AZ, US
Mitul B Modi - Phoenix AZ, US
Carolyn R. McCormick - Hillsboro OR, US
Ruben Cadena - Tempe AZ, US
Sankara J Subramanian - Chandler AZ, US
Edward L. Martin - Chandler AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/00

US Classification:

438106, 438107, 438108, 438109, 438123

Abstract:

An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.

US Patent:

20080057630, Mar 6, 2008

Filed:

Oct 26, 2007

Appl. No.:

11/978059

Inventors:

Mitul Modi - Phoenix AZ, US
Patricia Brusso - Chandler AZ, US
Ruben Cadena - Tempe AZ, US
Carolyn McCormick - Chandler AZ, US
Sankara Subramanian - Chandler AZ, US

International Classification:

H01L 21/00

US Classification:

438125000, 257700000, 257E23174

Abstract:

An IC package is disclosed that comprises a core region disposed between upper and lower build-up layer regions. In one embodiment, the core region comprises a low modulus material. In an alternative embodiment the core region comprises a medium modulus material. In an alternative embodiment, the core material is selected based upon consideration such as its modulus, its coefficient of thermal expansion, and/or resulting total accumulated strain. In an alternative embodiment, boundaries with respect to the softness of the core material are established by considering the relative density in opposing conductive build-up layers above and below the core region.

US Patent:

20130208411, Aug 15, 2013

Filed:

Mar 18, 2013

Appl. No.:

13/846218

Inventors:

Patricia A. Brusso - Chandler AZ, US
Mitul B. Modi - Phoenix AZ, US
Carolyn R. McCormick - Hillsboro OR, US
Ruben Cadena - Phoenix AZ, US
Sankara J. Subramanian - Chandler AZ, US
Edward L. Martin - Chandler AZ, US

International Classification:

H05K 1/11
G06F 1/16

US Classification:

36167902, 174264

Abstract:

An underfill device and method have been are provided. Advantages of devices and methods shown include dissipation of stresses at an interface between components such as a chip package and an adjacent circuit board. Another advantage includes faster manufacturing time and ease of manufacture using underfill devices and methods shown. An underfill assembly can be pre made with conductive structures included within the underfill assembly. Steps such as flowing epoxy and curing can be eliminated or performed concurrently with other manufacturing steps.