Bryan G Cope

US Patent:

6912608, Jun 28, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/131941

Inventors:

Edward A. Wolff - Chapel Hill NC, US
David Baker - Austin TX, US
Bryan Garnett Cope - Durham NC, US
Edwin Franklin Barry - Vilas NC, US

Assignee:

PTS Corporation - San Jose CA

International Classification:

G06F013/00

US Classification:

710100, 710 21, 712 10, 712 11, 711140, 345506

Abstract:

Techniques for a pipelined bus which provides a very high performance interface to computing elements, such as processing elements, host interfaces, memory controllers, and other application-specific coprocessors and external interface units. The pipelined bus is a robust interconnected bus employing a scalable, pipelined, multi-client topology, with a fully synchronous, packet-switched, split-transaction data transfer model. Multiple non-interfering transfers may occur concurrently since there is no single point of contention on the bus. An aggressive packet transfer model with local conflict resolution in each client and packet-level retries allows recovery from collisions and buffer backups. Clients are assigned unique IDs, based upon a mapping from the system address space allowing identification needed for quick routing of packets among clients.

US Patent:

6980056, Dec 27, 2005

Filed:

Nov 13, 2000

Appl. No.:

09/711770

Inventors:

Mark Alexander - Austin TX, US
Krishnan Subramonium - Austin TX, US
Golam Chowdhury - Austin TX, US
Kartika Prihadi - Austin TX, US
Bryan Cope - Austin TX, US

Assignee:

Cirrus Logic, Inc. - Austin TX

International Classification:

H03G003/10
H03G003/30

US Classification:

330284, 381120, 333 81 R

Abstract:

An attenuator includes a first stage having a first operational amplifier and a tapped resistor. Tapped resistor has an input for receiving input data, an output coupled to an output of first operational amplifier , and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of first operational amplifier. Each of these sequences of voltages corresponds to an attenuation step such that first stage steps the attenuation produced by the attenuator from an intermediate value to a predetermined ending value. A second stage includes a second operational amplifier and a tapped resistor. Tapped resistor includes an input for receiving analog data from first stage , an output coupled to an output of second operational amplifier , and a plurality of taps for selectively presenting a sequence of voltages to a noninverting input of operational amplifier. Each of the sequence of voltages corresponds to an attenuation step, a second stage stepping the attenuation from a predetermined starting value to the intermediate value.

US Patent:

7752373, Jul 6, 2010

Filed:

Feb 9, 2007

Appl. No.:

11/704656

Inventors:

Bryan Cope - Austin TX, US

Assignee:

Sigmatel, Inc. - Austin TX

International Classification:

G06F 13/14
G06F 13/00

US Classification:

710305, 710316, 711111

Abstract:

A system and method for controlling memory operations is disclosed. In a particular embodiment, the system includes a memory controller that can request control of a contact that is shared between a first memory device and a second memory device. In a particular embodiment, the memory controller includes a state machine to request and receive control of the contact. In another particular embodiment, the first memory device is a non-volatile memory device and the second memory device is a volatile memory device.

US Patent:

20080189479, Aug 7, 2008

Filed:

Feb 2, 2007

Appl. No.:

11/701628

Inventors:

Bryan Cope - Austin TX, US
Tauseef Rab - Austin TX, US
David Cureton Baker - Austin TX, US

Assignee:

SIGMATEL, INC. - Austin TX

International Classification:

G06F 13/00
G06F 13/36
G06F 12/00

US Classification:

711104, 710111, 710306, 711E12001

Abstract:

A device, system and method for controlling memory operations are disclosed. In an embodiment, data is received at one of multiple slave devices in an integrated circuit. The data is received from at least one bus in a multiple layer bus and is provided to a memory controller. The data is stored in a selected one of multiple memory banks. The memory banks are interleaved such that a first memory address resides on a first memory bank and a next memory address resides on a second memory bank.

US Patent:

62599577, Jul 10, 2001

Filed:

Apr 4, 1997

Appl. No.:

8/833185

Inventors:

Mark Alexander - Austin TX
Krishnan Subramonium - Austin TX
Golam Chowdhury - Austin TX
Kartika Prihadi - Austin TX
Bryan Cope - Austin TX

Assignee:

Cirrus Logic, Inc.

International Classification:

G06F 1700
H04B 100

US Classification:

700 94

Abstract:

Audio data processing circuitry 300 includes a plurality of analog inputs 101 for receiving analog audio data and a digital input 105 for receiving digital audio data. A analog mixer 312 mixes analog data received at said plurality of analog inputs 101 to generate a mixed analog audio stream. An analog-to-digital converter 313 converts the mixed analog audio stream to a digital audio stream and a digital mixer 315 mixes digital data received at the digital input 105 with the digital audio stream from the analog mixer 312 to generate a mixed digital audio stream.

US Patent:

20190190520, Jun 20, 2019

Filed:

Feb 7, 2019

Appl. No.:

16/270323

Inventors:

- Westlake Village CA, US
Gopal Raghavan - Thousand Oaks CA, US
Ben Wiley Melton - Thousand Oaks CA, US
Vidura Manu Wijayasekara - Thousand Oaks CA, US
Bryan Garnett Cope - Austin TX, US
David Cureton Baker - Austin TX, US
John Whitaker Havlicek - Thousand Oaks CA, US

International Classification:

H03K 19/003
H03K 19/017
H03K 19/177

Abstract:

There is disclosed a self-timed processor. The self-timed processor includes a plurality of functional blocks comprising null convention logic. Each of the functional blocks outputs one or more multi-rail data values. A global acknowledge tree generates a global acknowledge signal provided to all of the plurality of functional blocks. The global acknowledge signal switches to a first state when all of the multi-rail data values output from the plurality of functional blocks are in respective valid states, and the global acknowledge signal switches to a second state when all of the multi-rail data values output from the plurality of functional blocks are in a null state.

US Patent:

20190004811, Jan 3, 2019

Filed:

Jun 28, 2018

Appl. No.:

16/022443

Inventors:

- Westlake Village CA, US
Bryan Garnett Cope - Austin TX, US

International Classification:

G06F 9/38
G06F 1/32
G06F 17/50

Abstract:

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.

US Patent:

20190004812, Jan 3, 2019

Filed:

Jun 28, 2018

Appl. No.:

16/022524

Inventors:

- Westlake Village CA, US
Bryan Garnett Cope - Austin TX, US

International Classification:

G06F 9/38
H03K 19/00
G06F 17/50
H03K 19/20
G06F 1/32

Abstract:

There is disclosed a self-timed processor. The self-timed processor includes combinatorial logic comprising multi-rail delay insensitive asynchronous logic (DIAL) to output one or more multi-rail data values to a multiplexer. It also includes a test pattern input to output a test pattern bit stream of multi-rail test data values to the multiplexer. The multiplexer has Boolean logic to output one or more multi-rail multiplexed values to a latch. The multiplexer also has a single rail selector input to select whether the multi-rail multiplexed values are the multi-rail data values or the multi-rail test data values.