Bruce Lyle Hancock

Address:

214 Arbor Wood Cir, Oldsmar, FL 34677

VIN:

1FMEU51847UA12839

Make:

FORD

Model:

EXPLORER SPORT TRAC

Year:

2007

US Patent:

6519371, Feb 11, 2003

Filed:

Oct 2, 2000

Appl. No.:

09/677972

Inventors:

Bedabrata Pain - Los Angeles CA
Chao Sun - San Marino CA
Guang Yang - West Covina CA
Thomas J. Cunningham - Pasadena CA
Bruce Hancock - Altadena CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G06K 936

US Classification:

382288, 348171

Abstract:

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

US Patent:

6721464, Apr 13, 2004

Filed:

Jan 3, 2003

Appl. No.:

10/336701

Inventors:

Bedabrata Pain - Los Angeles CA
Chao Sun - San Marino CA
Guang Yang - West Covina CA
Thomas J. Cunningham - Pasadena CA
Bruce Hancock - Altadena CA

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

G06K 920

US Classification:

382312, 348294

Abstract:

A centroid computation system is disclosed. The system has an imager array, a switching network, computation elements, and a divider circuit. The imager array has columns and rows of pixels. The switching network is adapted to receive pixel signals from the image array. The plurality of computation elements operates to compute inner products for at least x and y centroids. The plurality of computation elements has only passive elements to provide inner products of pixel signals the switching network. The divider circuit is adapted to receive the inner products and compute the x and y centroids.

US Patent:

7019345, Mar 28, 2006

Filed:

Nov 16, 2001

Appl. No.:

10/008568

Inventors:

Bedabrata Pain - Los Angeles CA, US
Thomas J. Cunningham - Pasadena CA, US
Bruce Hancock - Altadena CA, US
Suresh Seshadri - Cerritos CA, US
Monico Ortiz - South Pasadena CA, US
Guang Yang - Annadale NJ, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 31/062
H01L 31/113

US Classification:

257292, 257290, 257291

Abstract:

The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

US Patent:

7235771, Jun 26, 2007

Filed:

Jul 27, 2005

Appl. No.:

11/191603

Inventors:

Bedabrata Pain - Los Angeles CA, US
Thomas J. Cunningham - Pasadena CA, US
Bruce R. Hancock - Altadena CA, US

Assignee:

California Institute of Technology - Malibu CA

International Classification:

H01L 27/00

US Classification:

2502081, 250214 R

Abstract:

A multiple-step reset process and circuit for resetting a voltage stored on a photodiode of an imaging device. A first stage of the reset occurs while a source and a drain of a pixel source-follower transistor are held at ground potential and the photodiode and a gate of the pixel source-follower transistor are charged to an initial reset voltage having potential less that of a supply voltage. A second stage of the reset occurs after the initial reset voltage is stored on the photodiode and the gate of the pixel source-follower transistor and the source and drain voltages of the pixel source-follower transistor are released from ground potential thereby allowing the source and drain voltages of the pixel source-follower transistor to assume ordinary values above ground potential and resulting in a capacitive feed-through effect that increases the voltage on the photodiode to a value greater than the initial reset voltage.

US Patent:

7746383, Jun 29, 2010

Filed:

Feb 12, 2004

Appl. No.:

10/779144

Inventors:

Bedabrata Pain - Los Angeles CA, US
Thomas J. Cunningham - Pasadena CA, US
Bruce Hancock - Altadena CA, US
Suresh Seshadri - Cerritos CA, US
Monico Ortiz - Goleta CA, US
Guang Yang - Annandale NJ, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H04N 5/225
H04N 5/217
H04N 3/14
H04N 5/335

US Classification:

3482161, 348241, 348308

Abstract:

The present invention provides a CMOS imager with a reset scheme, by which a CMOS imager generates a sub-kTC noise so that read noise does not depend on the sense node capacitance. By using a column feedback circuit, reset noise can be suppressed to a negligible amount so that photogate APS or CCD-like circuits can achieve noise performance to very efficient value. This scheme allows increasing sense node capacitance without increasing the noise and also achieves a large full-well value without sacrificing read noise performance. The feedback circuit in one of the embodiment of the present invention is located at the column side of the circuit. This design provides a minimal change to the pixel. As a result quantum efficiency or pixel size is not compromised. The present invention allows a CMOS imager to capture scene with high intra-scene contracts under low illumination with high dynamic range.

US Patent:

8164663, Apr 24, 2012

Filed:

Jun 16, 2006

Appl. No.:

11/454342

Inventors:

Bedabrata Pain - Los Angeles CA, US
Bruce Hancock - Altadena CA, US
Thomas J. Cunningham - Pasadena CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H04N 3/14
H04N 5/335

US Classification:

348294, 348308, 348319

Abstract:

For a source-follower signal chain, the ohmic drop in the selection switch causes unacceptable voltage offset, non-linearity, and reduced small signal gain. For an op amp signal chain, the required bias current and the output noise rises rapidly with increasing the array format due to a rapid increase in the effective capacitance caused by the Miller effect boosting up the contribution of the bus capacitance. A new switched source-follower signal chain circuit overcomes limitations of existing op-amp based or source follower based circuits used in column multiplexers and data readout. This will improve performance of CMOS imagers, and focal plane read-out integrated circuits for detectors of infrared or ultraviolet light.

US Patent:

8481907, Jul 9, 2013

Filed:

Jan 18, 2008

Appl. No.:

12/009595

Inventors:

Suresh Seshadri - West Covina CA, US
David Cole - Glendale CA, US
Roger M Smith - LaCanada Flintridge CA, US
Bruce R. Hancock - Pasadena CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H01L 27/00
H01J 40/14

US Classification:

2502081, 250214 R

Abstract:

The effects of inter pixel capacitance in a pixilated array may be measured by first resetting all pixels in the array to a first voltage, where a first image is read out, followed by resetting only a subset of pixels in the array to a second voltage, where a second image is read out, where the difference in the first and second images provide information about the inter pixel capacitance. Other embodiments are described and claimed.

US Patent:

8624769, Jan 7, 2014

Filed:

Aug 10, 2012

Appl. No.:

13/572098

Inventors:

Christopher James Wrigley - La Crescenta CA, US
Bruce R. Hancock - Altadena CA, US
Kenneth W. Newton - Castaic CA, US
Thomas J. Cunningham - Pasadena CA, US

Assignee:

California Institute of Technology - Pasadena CA

International Classification:

H03M 1/12

US Classification:

341155, 341169

Abstract:

An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.