Bruce A Fleming

Author:

Bruce W. Fleming

ISBN #:

0685501086

Author:

Bruce W. Fleming

ISBN #:

0773497919

Author:

Bruce Fleming

ISBN #:

0415953529

Author:

Bruce Fleming

ISBN #:

0415953537

Author:

Bruce Fleming

ISBN #:

0761832998

Author:

Bruce E. Fleming

ISBN #:

0820419125

Author:

Bruce E. Fleming

ISBN #:

0820427403

Author:

Bruce E. Fleming

ISBN #:

0820427861

US Patent:

7853748, Dec 14, 2010

Filed:

Sep 30, 2008

Appl. No.:

12/242293

Inventors:

Bruce Fleming - Morgan Hill CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/36
G06F 13/20
G06F 3/00

US Classification:

710311, 710 19, 710105, 710308, 710310, 710313

Abstract:

A method and apparatus are provided that include creating an image of a page descriptor at a universal serial bus (USB) device, transferring the image of the page descriptor to a main memory, modifying a schedule list in a main memory based on the transferred image, identifying an active transaction in the modified schedule list, and providing code data to the USB device from the main memory based on the identified active transaction.

US Patent:

7895370, Feb 22, 2011

Filed:

Dec 31, 2008

Appl. No.:

12/347066

Inventors:

Bruce Fleming - Morgan Hill CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 3/00

US Classification:

710 18, 713320

Abstract:

An apparatus and method are provided that include providing a transaction data structure, and monitoring the transaction data structure for a predetermined amount of time. A link between a bus device and a host controller may be provided into a low power state in response to the monitored transaction data structure.

US Patent:

8352770, Jan 8, 2013

Filed:

Sep 25, 2009

Appl. No.:

12/567707

Inventors:

Bruce L. Fleming - Morgan Hill CA, US
Ashish V. Choubal - Austin TX, US
Sanjoy K. Mondal - Austin TX, US
Belliappa M. Kuttanna - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713324, 713300, 713320

Abstract:

A method and system for saving and/or retrieving context information of a processor core for a power state transition. The processor core resides in a complex power domain variously transitioning between a plurality of power states. The processor core includes a local context storage area for storage and retrieval of processor core context information. A low power context storage resides in a nominal power domain external to the complex power domain. Context information of the processor core is stored to the low power context storage based on whether a power state transition of the complex power domain includes a transition to power down the processor core.

US Patent:

8380908, Feb 19, 2013

Filed:

Dec 31, 2009

Appl. No.:

12/650580

Inventors:

Bruce L. Fleming - Morgan Hill CA, US
Arvind Mandhani - San Francisco CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 13/24

US Classification:

710262, 710260, 710261, 710266

Abstract:

Embodiments of systems, apparatuses, and methods for emulating an input/output Advanced Programmable Interrupt Controller are disclosed. In one embodiment, an apparatus includes a first interrupt controller having a first programming model, and emulation logic to emulate a second interrupt controller having a second programming model that is different from the first programming model. The emulation logic is also to mask one of a plurality of interrupt requests to the first interrupt controller for each of the plurality of interrupt requests handled by the emulation logic.

US Patent:

8601304, Dec 3, 2013

Filed:

Mar 31, 2011

Appl. No.:

13/077882

Inventors:

Rajeev D. Muralidhar - Bangalore, IN
Harinarayanan Seshadri - Bangalore, IN
Bruce L. Fleming - Morgan Hill CA, US
Vishwesh M. Rudramuni - Bangalore, IN

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1/00

US Classification:

713323

Abstract:

Techniques to tie a processor power state transition on a platform to another power state transition on the platform. In an embodiment, processor governor functionality of an operating system detects an idle condition of a processor executing the operating system. Based on the processor idle condition and one or more indicated conditions of other platform devices, tying logic may determine a system power state to transition the platform to. For example, the tying logic may select from one of a plurality of idle standby system power states.

US Patent:

20100332902, Dec 30, 2010

Filed:

Jun 30, 2009

Appl. No.:

12/459295

Inventors:

Rajesh Banginwar - Hillsboro OR, US
Rajesh Kapoor - El Dorado Hills CA, US
Bruce L. Fleming - Santa Clara CA, US

International Classification:

G06F 11/14
G06F 1/26
G06F 11/30
G06F 11/07

US Classification:

714 23, 713300, 714 47, 714 2, 714E11023, 714E11113, 714E11179

Abstract:

An electronic device comprises a first processor, a computer readable memory medium and logic instructions stored in the computer readable medium which, when executed by the first processor, configure the first processor to implement a watchdog module which monitors an operating status of one or more critical processes executing on the first processor and implements a recovery process when the one or more of the critical processes executing on the first processor fails. The device further comprises a system controller unit coupled to the first processor by a communication bus, wherein system controller unit activates the watchdog module periodically and only when the first processor is in at least one predetermined power state. Other embodiments may be described.

US Patent:

20120166172, Jun 28, 2012

Filed:

Dec 23, 2010

Appl. No.:

12/977698

Inventors:

Bruce L. Fleming - Morgan Hill CA, US
Arvin Mandhani - San Francisco CA, US
Achmed A. Zahir - Menlo Park CA, US
Satish B. Acharya - Bangalore, IN

International Classification:

G06F 13/12

US Classification:

703 21

Abstract:

In some embodiments if a transaction is directed at existing hardware, then the transaction is directed to existing hardware. If the transaction is not directed at existing hardware, then the transaction is sent through a behavioral model. Other embodiments are described and claimed.

US Patent:

20120166779, Jun 28, 2012

Filed:

Mar 29, 2011

Appl. No.:

13/075057

Inventors:

Rajeev D. Muralidhar - Bangalore, IN
Harinarayanan Seshadri - Bangalore, IN
Bruce L. Fleming - Morgan Hill CA, US
Vishwesh M. Rudramuni - Bangalore, IN

International Classification:

G06F 15/177

US Classification:

713 1

Abstract:

Techniques to provide processor state for implementing a power state transition of a processor. In an embodiment, an operating system executing on a processor detects an opportunity to transition the processor to an idle processor power state. In particular embodiments, the operating system initiates the transition by invoking a task switch, wherein information describing a state of the processor is saved to a task switch segment.