Brian W Abernethy

US Patent:

47360739, Apr 5, 1988

Filed:

Feb 10, 1986

Appl. No.:

6/828060

Inventors:

Brian L. Abernethy - Glendale AZ

Assignee:

Sanders Associates, Inc. - Nashua NH

International Classification:

G08C 2100

US Classification:

178 19

Abstract:

A digitizing tablet (10) has common return lines (24, 25, 26, and 27) that tend to suppress sensing of the spurious signals induced in them when the digitizer probe (12) approaches the edge of a digitizing area (14). Each return line includes a connection segment (36) and a compensation segment (40), which extend in antiparallel along the edge of the digitizing area (14). The compensation segment (40) is spaced farther from the digitizing area than the connection segment (36) is so that it is only half as sensitive as the connection segment to probe signals. However, since only half of the emf induced in the connection segment (36) is coupled to the circuitry (22) for processing the induced signals, the signals induced in the return lines tend to cancel.

US Patent:

50456458, Sep 3, 1991

Filed:

May 22, 1990

Appl. No.:

7/527027

Inventors:

Jason Hoendervoogt - Phoenix AZ
Brian Abernethy - Phoenix AZ

Assignee:

CalComp Inc. - Anaheim CA

International Classification:

G08C 2100

US Classification:

178 19

Abstract:

A driving grid is driven by an ac signal comprising a carrier frequency modulated by a lower frequency. An untethered, batteryless pointer includes a pick-up coil in a first tuned circuit tuned to the carrier frequency, connected by diodes to a driving coil in a second tuned circuit tuned to the lower modulating frequency. Energy picked up by the first tuned circuit from the driving grid at the carrier frequency drives the second tuned circuit at the modulating frequency. Modulating frequency signals induced in the receiving grid conductors are used to locate the pointer in the usual manner. Because the carrier signal contains no frequency component of the modulating signal, the driving grid and receiving grid are sufficiently decoupled.

US Patent:

53845544, Jan 24, 1995

Filed:

Dec 8, 1993

Appl. No.:

8/163964

Inventors:

Brian Abernethy - Phoenix AZ

Assignee:

CalComp Inc. - Anaheim CA

International Classification:

H03K 303

US Classification:

331153

Abstract:

An integrated voltage controlled oscillator (VCO) circuit which utilizes the relative capacitance ratio between capacitors and the relative resistance ratio between resistors in an integrated circuit (IC) to output a signal having a predictable frequency for a given control signal voltage. The VCO output frequency will not vary more than 3. 0% from one IC chip implementing the VCO circuit, to the next. This low variance between IC chips is derived from the phenomenon whereby the respective ratios of capacitance and resistance between capacitors and resistors in the IC will not vary more than. +-. 1. 5% from the ratios of like capacitors and resistors on other IC chips. The integrated VCO circuit includes a control signal subcircuit, integrator subcircuit, filter subcircuit, and comparator unit subcircuit.