Brett Earl Forejt

US Patent:

6788146, Sep 7, 2004

Filed:

Dec 16, 2002

Appl. No.:

10/320123

Inventors:

Brett E. Forejt - Frisco TX
John M. Muza - Plano TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 345

US Classification:

330257, 330292

Abstract:

A Miller-compensated amplifier circuit. The circuit includes an amplifier stage, and a compensation capacitor arranged in parallel with the amplifier stage. A current multiplier circuit path, adapted to multiply a current through the compensation capacitor, includes an inversion stage in the current multiplier circuit path. The inversion stage includes a first current mirror adapted to mirror a first current corresponding to a current through the compensation capacitor, to provide a second current, as well as a second current mirror adapted to mirror and invert the second current to provide a third current and to apply the third current to the amplifier stage. In this way, the circuit is Miller compensated by only a single capacitor that has its capacitance multiplied in accordance with current-mode multiplication.

US Patent:

6943717, Sep 13, 2005

Filed:

Sep 30, 2004

Appl. No.:

10/955113

Inventors:

Brett E. Forejt - Plano TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M003/00

US Classification:

341143

Abstract:

A sigma delta class D device that uses a low pass filter to smooth the output waveform and eliminate high frequency switching noise from the feedback value includes: a first summing node having a positive input coupled to a signal input node; a second summing node having a first positive input coupled to an output of the first summing node and having an output coupled to a signal output node; a low pass filter having an input coupled to the output of the second summing node; an analog to digital converter having an input coupled to an output of the low pass filter; a third summing node having a positive input node coupled to an output of the analog to digital converter and a negative input node coupled to the output of the first summing node; and a feedback device coupled between an output of the third summing node and a negative input of the first summing node.

US Patent:

7528760, May 5, 2009

Filed:

Jan 26, 2007

Appl. No.:

11/627635

Inventors:

Brett Forejt - Plano TX, US

Assignee:

Texas Insturments Incorporated - Dallas TX

International Classification:

H03M 1/50

US Classification:

341166, 341155

Abstract:

A new analog-to-digital (ADC) circuit and architecture and the corresponding method of implementation are provided. The analog input signal is converted into a modulated pulse stream such as by a pulse-width-modulation scheme. The time-duration width of the pulses are measured by a TDC (time-to-digital converter) and converted to a digital binary representation that is directly correlated with the voltage amplitude of the analog input signal. The circuit implementation is substantially free of switches and circuit issues such as associated with sigma-delta and switched-capacitor techniques for ADC's.

US Patent:

7679444, Mar 16, 2010

Filed:

Oct 27, 2008

Appl. No.:

12/259024

Inventors:

Brett Forejt - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330258, 330252

Abstract:

One embodiment of the invention includes a differential amplifier circuit. A first input stage generates first and second control voltages in response to a differential input signal. A second input stage generates third and fourth control voltages in response to the differential input signal. The first and second control voltages can be inversely proportional and the third and fourth control voltages can be inversely proportional. The circuit also includes a first output stage that is configured to set a magnitude of a first output voltage of a differential output signal at a first output node in response to the first and second control voltages. The circuit further includes a second output stage that is configured to set a magnitude of a second output voltage of the differential output signal at a second output node in response to the third and fourth control voltages.

US Patent:

7733179, Jun 8, 2010

Filed:

Oct 21, 2008

Appl. No.:

12/288481

Inventors:

Brett E. Forejt - Garland TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330258, 330 9, 330253

Abstract:

A differential amplifier (-) includes an input stage () including first (M) and second (M) input transistors and first (A) and second (B) load devices. Sources of the first and second input transistors are connected together. Drains of the first and second input transistors are coupled by first () and second () conductors to the first and second load devices, respectively. Common mode feedback circuitry (A) including first (M), second (M), and third (M) transistors is combined with offset correction circuitry () including the second transistor and the third transistor. Sources of the first, second, and third transistors are coupled to a tail current source (). Drains of the second and third transistors are coupled to the first and second conductors, respectively. A common mode voltage (V) is applied to a gate of the first transistor. Offset trim voltages are applied to gates of the second and third transistors.

US Patent:

8008969, Aug 30, 2011

Filed:

Mar 30, 2010

Appl. No.:

12/750494

Inventors:

Brett E. Forejt - Garland TX, US
David J. Baldwin - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/38

US Classification:

330 10, 330251, 330207 A, 330302

Abstract:

Traditionally, switching amplifiers (i. e. , class-D and class-G) with negative supply rails had issues with direct current (DC) power loss, included large external capacitors, had a comparative reduction in efficiency, and oftentimes included separate power management circuits. Here, a class-D amplifier is provided with an output stage that provides negative supply voltages, positive supply voltages, and ground. Essentially, this amplifier provides some of the benefits of the conventional amplifiers without the drawbacks.

US Patent:

8350623, Jan 8, 2013

Filed:

Mar 14, 2011

Appl. No.:

13/047505

Inventors:

Brett Forejt - Garland TX, US
Jeff Berwick - Sunnyvale TX, US
David J. Baldwin - Allen TX, US

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03F 3/45

US Classification:

330254, 330284

Abstract:

An apparatus and method are provided. Generally, an input signal is applied across a main path (through an input network) and across a cancellation path (through a cancellation circuit). The cancellation circuit subtracts a cancellation current from the main path as part of the control mechanism, where the magnitude of the cancellation current is based on a gain control signal (that has been linearized to follow a control voltage).

US Patent:

20020060607, May 23, 2002

Filed:

Nov 20, 2001

Appl. No.:

09/988474

Inventors:

Brett Forejt - Frisco TX, US

International Classification:

H03F003/45

US Classification:

330/253000

Abstract:

A circuit and method is provided that provides an amplification stage to a comparator device that matches transistor transconductances to provide adequate amplification and employs diode coupled transistors to control the common mode output bias voltage. The circuit and method provides for a high gain comparator stage with control over output common mode voltage, while providing rail to rail output swing during differential mode without an external feedback to the comparator device.