Brett S Feero

US Patent:

20120331197, Dec 27, 2012

Filed:

Jun 24, 2011

Appl. No.:

13/067775

Inventors:

Michael Andrew Campbell - Waterbeach, GB
Christopher Edwin Wrigley - Saffron Walden, GB
Brett Stanley Feero - Austin TX, US

International Classification:

G06F 13/362

US Classification:

710117

Abstract:

A memory controller is for controlling access to a memory device of the type having a non-uniform access timing characteristic. An interface receives transactions issued from at least one transaction source and a buffer temporarily stores as pending transactions those transactions received by the interface that have not yet been issued to the memory device. The buffer maintains a plurality of ordered lists (having a number of entries) for the stored pending transactions, including at least one priority based ordered list and at least one access timing ordered list. Each entry being associated with one of the pending transactions, and ordered within its priority based ordered list based on the priority indication of the associated pending transaction. Arbitration circuitry performs an arbitration operation during which the plurality of ordered lists are referenced so as to select a winning transaction to be issued to the memory device.

US Patent:

20130042070, Feb 14, 2013

Filed:

Aug 8, 2011

Appl. No.:

13/137357

Inventors:

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Michael Alan Filippo - Driftwood TX, US

Assignee:

ARM LIMITED - Cambridge

International Classification:

G06F 12/08

US Classification:

711130, 711E12038, 711E12033

Abstract:

A data processing system includes a cache hierarchy having a plurality of local cache memories and a shared cache memory State data stored within the shared cache memory on a per cache line basis is used to control whether or not that cache line of data is stored and managed in accordance with non-inclusive operation or inclusive operation of the cache memory system. Snoop transactions are filtered on the basis of data indicating whether or not a cache line of data is unique or non-unique. A switch from non-inclusive operation to inclusive operation may be performed in dependence upon the transaction type of a received transaction requesting a cache line of data.

US Patent:

20130042078, Feb 14, 2013

Filed:

Aug 8, 2011

Appl. No.:

13/137359

Inventors:

Jamshed Jalal - Austin TX, US
Brett Stanley Feero - Austin TX, US
Mark David Werkheiser - Austin TX, US
Michael Alan Filippo - Driftwood TX, US

International Classification:

G06F 12/08

US Classification:

711146, 711E12033

Abstract:

A data processing apparatus includes a plurality of transaction sources each including a local cache memory. A shared cache memory stores cache lines of data together with shared cache tag values. Snoop filter circuitry stores snoop filter tag values tracking which cache lines of data are stored within the local cache memories. When a transaction is received for a target cache line of data, then the snoop filter circuitry compares the target tag value with the snoop filter tag values and the shared cache circuitry compares the target tag value with the shared cache tag values. The shared cache circuitry operates in a default non-inclusive mode. The shared cache memory and the snoop filter accordingly behave non-inclusively in respect of data storage within the shared cache memory but inclusively in respect of tag storage given the combined action of the snoop filter tag values and the shared cache tag values. Tag maintenance operations moving tag values between the snoop filter circuitry and the shared cache memory are performed atomically. The snoop filter circuitry and the shared cache memory compare operations are performed using interlocked parallel pipelines.

US Patent:

20130042249, Feb 14, 2013

Filed:

Aug 8, 2011

Appl. No.:

13/137362

Inventors:

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Michael Alan Filippo - Driftwood TX, US
Ramamoorthy Guru Prasadh - Austin TX, US
Phanindra Kumar Mannava - Austin TX, US

Assignee:

ARM Limited - Cambridge

International Classification:

G06F 9/46

US Classification:

718103

Abstract:

An integrated circuit includes a plurality of transaction sources communicating via a ring-based interconnect with shared caches each having an associated POC/POS and serving as a request servicing circuit. The request servicing circuits have a set of processing resources that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

US Patent:

20130042252, Feb 14, 2013

Filed:

Aug 8, 2011

Appl. No.:

13/137360

Inventors:

Jamshed Jalal - Austin TX, US
Mark David Werkheiser - Austin TX, US
Brett Stanley Feero - Austin TX, US
Ramamoorthy Guru Prasadh - Austin TX, US
Michael Alan Filippo - Driftwood TX, US
Phanindra Kumar Mannava - Austin TX, US

Assignee:

ARM LIMITED - Cambridge

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

An integrated circuit includes a plurality of transaction sources communicating via a ring-based interconnect with shared caches each having an associated POC/POS and serving as a request servicing circuit. The request servicing circuits have a set of processing resources that may be allocated to different transactions. These processing resources may be allocated either dynamically or statically. Static allocation can be made in dependence upon a selection algorithm. This selection algorithm may use a quality of service value/priority level as one of its input variables. A starvation ratio may also be defined such that lower priority levels are forced to be selected if they are starved of allocation for too long. A programmable mapping may be made between quality of service values and priority levels. The maximum number of processing resources allocated to each priority level may also be programmed.

US Patent:

20200371812, Nov 26, 2020

Filed:

Aug 12, 2020

Appl. No.:

16/991858

Inventors:

- Cupertino CA, US
Brett S. Feero - Austin TX, US
Nikhil Gupta - Santa Clara CA, US

International Classification:

G06F 9/38
G06F 12/0815
G06F 12/084

Abstract:

In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.

US Patent:

20200218540, Jul 9, 2020

Filed:

Jan 8, 2019

Appl. No.:

16/242151

Inventors:

- Cupertino CA, US
Brett S. Feero - Austin TX, US
Nikhil Gupta - Santa Clara CA, US
Viney Gautam - San Jose CA, US

International Classification:

G06F 9/38
G06F 9/30
G06F 9/48
G06F 9/52

Abstract:

In an embodiment, a processor includes a buffer in an interface unit. The buffer may be used to accumulate coprocessor instructions to be transmitted to a coprocessor. In an embodiment, the processor issues the coprocessor instructions to the buffer when ready to be issued to the coprocessor. The interface unit may accumulate the coprocessor instructions in the buffer, generating a bundle of instructions. The bundle may be closed based on various predetermined conditions and then the bundle may be transmitted to the coprocessor. If a sequence of coprocessor instructions appears consecutively in a program, the rate at which the instructions are provided to the coprocessor (on average) at least matches the rate at which the coprocessor consumes the instructions, in an embodiment.

US Patent:

20200183736, Jun 11, 2020

Filed:

Dec 5, 2018

Appl. No.:

16/210231

Inventors:

- Cupertino CA, US
Brett S. Feero - Austin TX, US
Nikhil Gupta - Santa Clara CA, US

International Classification:

G06F 9/48
G06F 9/30
G06F 9/38
G06F 12/0815

Abstract:

In an embodiment, at least one CPU processor and at least one coprocessor are included in a system. The CPU processor may issue operations to the coprocessor to perform, including load/store operations. The CPU processor may generate the addresses that are accessed by the coprocessor load/store operations, as well as executing its own CPU load/store operations. The CPU processor may include a memory ordering table configured to track at least one memory region within which there are outstanding coprocessor load/store memory operations that have not yet completed. The CPU processor may delay CPU load/store operations until the outstanding coprocessor load/store operations are complete. In this fashion, the proper ordering of CPU load/store operations and coprocessor load/store operations may be maintained.