Brett Warren Coon

US Patent:

6356615, Mar 12, 2002

Filed:

Oct 13, 1999

Appl. No.:

09/417930

Inventors:

Brett Coon - Milpitas CA
David Keppel - Seattle WA
Charles R. Price - Sunnyvale CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G07C 300

US Classification:

377 16, 377 2

Abstract:

Certain events occurring throughout a microprocessor chip are monitored by a counter system ( ) containing a number of digital electronic counters ( ) consolidated at a single location on the processor chip. Those events are communicated to the counter system via electrical leads extending to those functional units in the processor responsible for signaling an event occurrence. Under program control, each counter can be selectively connected ( ) to a selected one of the various functional event producing units. By means of selection logic ( ) separate events originating from multiple functional units may be logically combined, whereby the event counted is a Boolean logic combination of multiple underlying events.

US Patent:

6604188, Aug 5, 2003

Filed:

Oct 20, 1999

Appl. No.:

09/421972

Inventors:

Brett Coon - Milpitas CA
Godfrey DSouza - San Jose CA
Paul Serris - Sunnyvale CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 940

US Classification:

712 24, 712215

Abstract:

Instructions asserted in the instruction pipeline ( ) of the microprocessor are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( ) of the processor. The control information pipeline is synchronized to the instruction pipeline so that the control information for an instruction progresses in synchronism with the instruction. The control information may identify, directly or indirectly, the type of operation called for by the instruction and, if the operation is to be performed in parts, indicate the part to be performed. Means are included in the processor, such as a number of functional execution units ( ), to interpret that control information and take appropriate action. Applied in a VLIW processor to an atom operation that requires multiple cycles to complete, in which the first part of the operation is permitted to complete and the atom then reasserted, the control information identifies the second assertion of the atom as the second part of a multi-cycle operation.

US Patent:

6615300, Sep 2, 2003

Filed:

Jun 19, 2000

Appl. No.:

09/596279

Inventors:

John Banning - Sunnyvale CA
Brett Coon - Milpitas CA
Linus Torvalds - Santa Clara CA
Brian Choy - San Jose CA
Malcolm Wing - Menlo Park CA
Patrick Gainer - San Jose CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 906

US Classification:

710100, 711118, 711202, 712205

Abstract:

Dynamic translation of indirect branch instructions of a target application by a host processor is enhanced by including a cache to provide access to the addresses of the most frequently used translations of a host computer, minimizing the need to access the translation buffer. Each entry in the cache includes a host instruction address, a logical address of the instruction of the target application, the physical address of that instruction, the code segment limit to the instruction, and the context value of the host processor associated with that instruction, the last four named components constituting tags to the host instruction address, and a valid-invalid bit. In a basic embodiment, the cache is a software cache apportioned by software from the main processor memory chips.

US Patent:

6640297, Oct 28, 2003

Filed:

Jun 19, 2000

Appl. No.:

09/596280

Inventors:

John Banning - Sunnyvale CA
Brett Coon - Milpitas CA
Eric Hao - Cupertino CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 938

US Classification:

712238

Abstract:

The speed of processing of a sequence of indirect branch instructions in a pipelined processor is increased by overlapping the latencies in the sequence of indirect branch instructions. The architecture of a digital processor is modified to include a link pipe system that allows the sequence of branch addresses required by the indirect branches to be written to a single location within the processor, and to be read from a single location in the processor. The link pipe system contains a plurality of registers ( ) for storage of respective branch target addresses. Each WRITE of a branch address is automatically directed ( ) to individual registers within the link pipe system for storing the respective branch addresses; and each READ of a branch address is automatically directed ( ) to the register containing the earliest WRITE of an address that was not previously read by the processor, whereby branch target addresses are retrieved on a âfirst in, first outâ basis.

US Patent:

6728865, Apr 27, 2004

Filed:

Oct 20, 1999

Appl. No.:

09/420748

Inventors:

Brett Coon - Milpitas CA
Godfrey DSouza - San Jose CA
Paul Serris - Sunnyvale CA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

712204, 712 23, 712 24, 712218, 712222, 711201

Abstract:

Instructions asserted in a microprocessors instruction pipeline ( ) are accompanied by control information, comprising a group of bits, asserted within a control information pipeline ( ) that is synchronized to the instruction pipeline. At the execution stage, the control information is interpreted and appropriate action taken. The control information may indicate that the instruction has been reasserted (asserted again following an initial assertion) and may also indicate the number of times that the instruction has been consecutively asserted in the instruction pipeline. Applied to unaligned memory operations, in which a memory atom is asserted twice, the control information indicates which part of the unaligned data is to be fetched each time the atom is executed.

US Patent:

6738892, May 18, 2004

Filed:

Oct 20, 1999

Appl. No.:

09/421615

Inventors:

Brett Coon - Milpitas CA
David Keppel - Seattle WA

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F 1580

US Classification:

712 24, 712219, 712244

Abstract:

An information control pipeline ( ) parallels the processors instruction pipeline ( ), contains digital control information in respect of the instruction placed in the instruction pipeline and accompanies that instruction until all component operations prescribed within the instruction have been executed. When at the end of the pipeline, the instruction is presented for execution to a respective functional execution unit ( ) of the processor, the respective functional execution unit accesses and uses the control information as a condition to instruction execution. Depending upon the processor, the control information may contain one or more bits, referred to as enable bits, as may be set enabled, indicating that an associated operation in the instruction is to be executed, or by software set disabled, indicating that the associated operation is masked, such as by an exception handler ( ) when returning from a resolved exception.

US Patent:

6954847, Oct 11, 2005

Filed:

Feb 4, 2002

Appl. No.:

10/061295

Inventors:

Brett Coon - San Jose CA, US
Yoshiyuki Miyayama - Santa Clara CA, US
Le Trong Nguyen - Monte Sereno CA, US
Johannes Wang - Redwood City CA, US

Assignee:

Transmeta Corporation - Santa Clara CA

International Classification:

G06F009/30

US Classification:

712208, 712204, 712 23

Abstract:

A system and method for extracting complex, variable length computer instructions from a stream of complex instructions each subdivided into a variable number of instructions bytes, and aligning instruction bytes of individual ones of the complex instructions. The system receives a portion of the stream of complex instructions and extracts a first set of instruction bytes starting with the first instruction bytes, using an extract shifter. The set of instruction bytes are then passed to an align latch where they are aligned and output to a next instruction detector. The next instruction detector determines the end of the first instruction based on said set of instruction bytes. An extract shifter is used to extract and provide the next set of instruction bytes to an align shifter which aligns and outputs the next instruction. The process is then repeated for the remaining instruction bytes in the stream of complex instructions. The isolated complex instructions are decoded into nano-instructions which are processed by a RISC processor core.

US Patent:

7027062, Apr 11, 2006

Filed:

Feb 27, 2004

Appl. No.:

10/789735

Inventors:

John Erik Lindholm - Saratoga CA, US
John R. Nickolls - Los Altos CA, US
Simon S. Moy - Los Altos CA, US
Brett W. Coon - San Jose CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06T 11/40

US Classification:

345552, 345582, 345559

Abstract:

A graphics processing unit can queue a large number of texture requests to balance out the variability of texture requests without the need for a large texture request buffer. A dedicated texture request buffer queues the relatively small texture commands and parameters. Additionally, for each queued texture command, an associated set of texture arguments, which are typically much larger than the texture command, are stored in a general purpose register. The texture unit retrieves texture commands from the texture request buffer and then fetches the associated texture arguments from the appropriate general purpose register. The texture arguments may be stored in the general purpose register designated as the destination of the final texture value computed by the texture unit. Because the destination register must be allocated for the final texture value as texture commands are queued, storing the texture arguments in this register does not consume any additional registers.