Alan Lewis - Sunnyvale CA, US Brad Cantos - San Francisco CA, US Glen P. Carey - Palo Alto CA, US William R. Hitchens - Mountain View CA, US Jason P. Watson - San Jose CA, US Aram Mooradian - Kentfield CA, US
Assignee:
Novalux, Inc. - Sunnyvale CA
International Classification:
H01S 5/00
US Classification:
372 50124, 372 5012, 372 50122
Abstract:
An array of surface emitting laser diodes has a series electrical connection of laser diodes. Junction isolation is used to isolate laser diodes in the array.
Cavity And Packaging Designs For Arrays Of Vertical Cavity Surface Emitting Lasers With Or Without Extended Cavities
Jason Watson - San Jose CA, US Andrei Shchegrov - Campbell CA, US Aram Mooradian - Kentfield CA, US Kenneth Scholz - Palo Alto CA, US William Hitchens - Mountain View CA, US Brad Cantos - San Francisco CA, US John Green - Scotts Valley CA, US
Assignee:
Novalux, Inc. - Sunnyvale CA
International Classification:
H01S 5/00
US Classification:
372050124, 372050120
Abstract:
Arrays of surface emitting lasers are disclosed. A top contact plate is patterned with apertures and used to form an electrical connection to a top surface of a laser die. The top contact plate reduces electrical resistance and improves current uniformity compared with conventional contacts formed by plating.
Method Of Fabricating Microwave Fet Having Gate With Submicron Length
Walter A. Strifler - Cupertino CA Brad D. Cantos - San Francisco CA
Assignee:
Watkins Johnson Company - Palo Alto CA
International Classification:
H01L 21265
US Classification:
437 41
Abstract:
Disclosed is a method of forming a uniform length gate electrode and contact for a microwave field-effect transistor where the gate electrode has a length of less than one micron. A photoresist plug is formed on the surface of a first photoresist layer, the plug functioning as a shadow mask in the subsequent deposition of a plasma-etch-resistant material (aluminum) over the surface of the plug and the first photoresist layer. A third photoresist layer is formed over the device structure whereby a contact region can be formed on the surface of the semiconductor sub-strate adjacent to the device region. Subsequently, the third photoresist layer is removed, and the previously shielded photoresist material over the gate electrode location is removed by plasma etch using the metal-covered plug and metal-covered first photoresist layer as a plasma-etch shield. A metal is then deposited in the exposed surface region for the gate electrode and contact, and thereafter the photoresist material is removed leaving the gate electrode and contact on the substrate surface.
L-3 Communications Jan 2007 - Aug 2007
Senior Technical Consultant
Novalux, Inc May 2000 - Jan 2007
Director, Wafer & Die Operations
Pacific Consultants, LLC Sep 1998 - May 2000
Consultant
PixTech 1998 - 1999
Technical Staff
Education:
State University of New York at Buffalo
Skills:
Operations Management Start Up Ventures Grant Preparation Grants Program Management Managing Start Ups Start Up Consulting Vendor Management Process Engineering Semiconductor Process Compound Semiconductors Process Improvement Process Management Photolithography Product Development Outsourcing Testing Engineering Management Start Ups Management Lean Manufacturing Leadership Semiconductors Supply Chain Team Building Cross Functional Team Leadership Process Simulation Manufacturing Continuous Improvement Spc Purchasing Project Planning Telecommunications Optics
Interests:
Cooking and Wine Filemaker Pro Development Photography (Film and Digital) Travel Holography
Process engineer consulting for semiconductor and other related technology industries. Currently working on an NSF-sponsored project for green building products.