Bodo K Parady

US Patent:

6385657, May 7, 2002

Filed:

Apr 20, 2000

Appl. No.:

09/553600

Inventors:

Bodo K. Parady - Danville CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1516

US Classification:

709251, 709249, 709238, 370 88, 370222, 370223

Abstract:

A computer system employs a hierarchical ring structure for communication. Computer system elements are configured into modules with ring interface hardware, and the modules are coupled to one or more rings. Bridge modules may be included for transmitting between rings in the hierarchy. The rings are time division multiplexed, and each time slot on a ring carries a frame. According to an address carried within the frame, bridge modules determine whether or not to transmit a frame circulating on a source ring onto a target ring. If the address of the frame indicates a module upon the source ring, the bridge module retransmits the frame on the source ring. Otherwise, the bridge module transmits the frame on the target ring. The bridge module operates in this fashion at any level of the hierarchy. The owner of a time slot on a ring is permitted to release the time slot for use by other modules.

US Patent:

6408368, Jun 18, 2002

Filed:

Jun 15, 1999

Appl. No.:

09/333418

Inventors:

Bodo Parady - Danville CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1200

US Classification:

711159, 711163

Abstract:

A software methodology to control replacement of one or more selected pages within a cache memory in a computer system. The operating system designates one or more pages containing critical data, text or other digital information as hot pages within a physical system memory in the computer system and prevents replacement during execution of various application programs of these hot pages when cached. The operating system inhibits allocation of the conflict pages that would map to cache locations occupied by a cached hot page, thereby preserving the hot page within the cache memory. The conflict pages are placed at the bottom of a free list created in the system memory by the operating system. The operating system scans the free list using a pointer while allocating free system memory space at run-time. The system memory pages are allocated from the free list until the pointer reaches a conflict page.

US Patent:

6437653, Aug 20, 2002

Filed:

Sep 28, 2000

Appl. No.:

09/675115

Inventors:

Jose M. Cruz - Palo Alto CA
Bodo K. Parady - Danville CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

H03B 512

US Classification:

331181, 331 36 L, 331117 R, 331117 D, 331177 R, 331 96, 257531

Abstract:

One embodiment of the present invention provides an inductor with a variable inductance within a semiconductor chip. This inductor includes a primary spiral composed of a conductive material embedded within the semiconductor chip to provide a source of variable inductance. It also includes a control spiral composed of the conductive material vertically displaced from the primary spiral in neighboring layers of the semiconductor chip. This control spiral is magnetically coupled with the primary spiral so that changing a control current through the control spiral induces a change in inductance through the primary spiral. The inductor also includes a controllable current source coupled to the control spiral that is configured to provide the control current. One embodiment of the present invention includes a core surrounding the primary spiral and the control spiral in the semiconductor chip. This core is comprised of a core material with a magnetic permeability that facilitates magnetically coupling the control spiral with the primary spiral.

US Patent:

6578137, Jun 10, 2003

Filed:

Aug 8, 2001

Appl. No.:

09/925090

Inventors:

Bodo K. Parady - Danville CA

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 940

US Classification:

712228, 712205

Abstract:

A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

US Patent:

6859844, Feb 22, 2005

Filed:

Feb 20, 2002

Appl. No.:

10/079294

Inventors:

Bodo K. Parady - Danville CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F015/16
H04B007/212

US Classification:

709251, 370321, 370337, 365 78

Abstract:

A computer system comprises a plurality of modules and a shift register having a plurality of slots connected in series, wherein each of the plurality of slots is coupled to one of the plurality of modules. In one embodiment, an output of a last slot of the plurality of slots is coupled to an input of an initial slot of the plurality of slots to form a ring. Each slot of the shift register corresponds to a time slot on the ring, and each of the time slots is assigned to one of the modules. At least two of the modules are configured to independently generate frames for transmission on the ring. In another embodiment, at least one of the modules comprises a bridge module coupled to communicate with other bridge modules separate from the plurality of modules.

US Patent:

6907520, Jun 14, 2005

Filed:

Jan 11, 2002

Appl. No.:

10/044487

Inventors:

Bodo K. Parady - Danville CA, US

Assignee:

Sun Microsystems, Inc. - Santa Clara CA

International Classification:

G06F009/00

US Classification:

712228

Abstract:

A method and apparatus for predicting load addresses and identifying new threads of instructions for execution in a multithreaded processor. A load prediction unit scans an instruction window for load instructions. A load prediction table is searched for an entry corresponding to a detected load instruction. If an entry is found in the table, a load address prediction is made for the load instruction and conveyed to the data cache. If the load address misses in the cache, the data is prefetched. Subsequently, if it is determined that the load prediction was incorrect, a miss counter in the corresponding entry in the load prediction table is incremented. If on a subsequent detection of the load instruction, the miss counter has reached a threshold, the load instruction is predicted to miss. In response to the predicted miss, a new thread of instructions is identified for execution.

US Patent:

62956000, Sep 25, 2001

Filed:

Jun 28, 1999

Appl. No.:

9/340328

Inventors:

Bodo Parady - Danville CA

Assignee:

Sun Microsystems, Inc. - Palo Alto CA

International Classification:

G06F 1516

US Classification:

712228

Abstract:

A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.

US Patent:

59336277, Aug 3, 1999

Filed:

Jul 1, 1996

Appl. No.:

8/675627

Inventors:

Bodo Parady - Danville CA

Assignee:

Sun Microsystems - Palo Alto CA

International Classification:

G06F 1516
G06F 938

US Classification:

395569

Abstract:

A method and apparatus for switching between threads of a program in response to a long-latency event. In one embodiment, the long-latency events are load or store operations which trigger a thread switch if there is a miss in the level 2 cache. In addition to providing separate groups of registers for multiple threads, a group of program address registers pointing to different threads are provided. A switching mechanism switches between the program address registers in response to the long-latency events.