Wen Zhong Kong

US Patent:

8317910, Nov 27, 2012

Filed:

Mar 22, 2010

Appl. No.:

12/661678

Inventors:

Robin Cheung - Cupertino CA, US
Wen Zhong Kong - Newark CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

C23C 18/42

US Classification:

106 128

Abstract:

A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e. g. , electrical current) and does not require electrodes (e. g. , anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e. g. , catalytic converters), and irregularly shaped metal surfaces.

US Patent:

8361560, Jan 29, 2013

Filed:

Aug 16, 2012

Appl. No.:

13/587774

Inventors:

Robin Cheung - Cupertino CA, US
Wen Zhong Kong - Newark CA, US

Assignee:

Unity Semiconductor Corporation - Sunnyvale CA

International Classification:

B05D 1/02
B05D 1/18
C23C 18/42
B32B 15/01

US Classification:

427436, 106 128, 428670

Abstract:

A platinum plating solution for immersion plating a continuous film of platinum on a metal structure. The immersion platinum plating solution is free of a reducing agent. The plating process does not require electricity (e. g. , electrical current) and does not require electrodes (e. g. , anode and/or cathode). The solution includes a platinum source and a complexing agent including Oxalic Acid. The solution enables immersion plating of platinum onto a metal surface, a metal substrate, or a structure of which at least a portion is a metal. The resulting platinum plating comprises a continuous thin film layer of platinum having a thickness not exceeding 300 Å. The solution can be used for plating articles including but not limited to jewelry, medical devices, electronic structures, microelectronics structures, MEMS structures, nano-sized or smaller structures, structures used for chemical and/or catalytic reactions (e. g. , catalytic converters), and irregularly shaped metal surfaces.

US Patent:

20070284746, Dec 13, 2007

Filed:

Apr 30, 2007

Appl. No.:

11/742328

Inventors:

Sergey Lopatin - Santa Clara CA, US
Robert Fiordalice - Austin TX, US
Faivel Pintchovski - Austin TX, US
Igor Ivanov - Dublin CA, US
Wen Kong - Newark CA, US
Artur Kolics - Dublin CA, US

Assignee:

KLA-TENCOR TECHNOLOGIES CORPORATION - Milpitas CA

International Classification:

H01L 21/82

US Classification:

257752000, 977723000

Abstract:

An integrated circuit is provided including an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is over the dielectric layer in the trench and via, and a conductor is over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

US Patent:

20120012897, Jan 19, 2012

Filed:

Jul 18, 2011

Appl. No.:

13/185410

Inventors:

PAUL BESSER - SUNNYVALE CA, US
ROBIN CHEUNG - CUPERTINO CA, US
WEN ZHONG KONG - NEWARK CA, US

Assignee:

UNITY SEMICONDUCTOR CORPORATION - SUNNYVALE CA

International Classification:

H01L 23/52

US Classification:

257208, 257E23141

Abstract:

A non-Flash non-volatile cross-trench memory array formed using an array of trenches formed back-end-of-the-line (BEOL) over a front-end-of-the-line (FEOL) substrate includes two-terminal memory elements operative to store at least one bit of data that are formed at a cross-point of a first trench and a second trench. The first and second trenches are arranged orthogonally to each other. At least one layer of memory comprises a plurality of the first and second trenches to form a plurality of memory elements. The non-volatile memory can be used to replace or emulate other memory types including but not limited to embedded memory, DRAM, SRAM, ROM, and FLASH. The memory is randomly addressable down to the bit level and erase or block erase operation prior to a write operation are not required.

US Patent:

7226856, Jun 5, 2007

Filed:

Nov 15, 2004

Appl. No.:

10/990273

Inventors:

Sergey D. Lopatin - Santa Clara CA, US
Robert Fiordalice - Austin TX, US
Faivel Pintchovski - Austin TX, US
Igor Ivanov - Dublin CA, US
Wen Z. Kong - Newark CA, US
Artur Kolics - Dublin CA, US

Assignee:

KLA-Tencor Technologies Corporation - Milpitas CA

International Classification:

H01L 21/4763

US Classification:

438629, 977723, 438631

Abstract:

An integrated circuit and a method of manufacturing an integrated circuit is provided including providing an integrated circuit having a trench and via provided in a dielectric layer. A nano-electrode-array is formed over the dielectric layer in the trench and via, and a conductor is deposited over the nano-electrode-array. The conductor and the nano-electrode-array are coplanar with a surface of the dielectric layer.

US Patent:

20140346035, Nov 27, 2014

Filed:

May 23, 2014

Appl. No.:

14/286841

Inventors:

- Fremont CA, US
Wen Zhong Kong - Newark CA, US

International Classification:

C25D 17/00

US Classification:

204222, 20429701, 20429714, 204242, 2042751

Abstract:

One embodiment provides an electroplating apparatus, which includes a tank filled with an electrolyte solution, a number of anodes situated around edges of the tank, a cathode situated above the tank, and a plurality of wafer-holding jigs attached to the cathode. A respective wafer-holding jig includes a common connector electrically coupled to the cathode and a pair of wafer-mounting frames electrically coupled to the common connector. Each wafer-mounting frame includes a plurality of openings, and a respective opening provides a mounting space for a to-be-plated solar cell, thereby facilitating simultaneous plating of front and back surfaces of the plurality of the solar cells.