Bing B Dang from 85 Park Dr, Chappaqua, NY 10514, age 50, Phone: 914 356-2991

Us Patents

Integrated Module For Data Processing System
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US Patent:

7750459, Jul 6, 2010
Filed:

Feb 1, 2008
Appl. No.:

12/024394
Inventors:

Bing Dang - Ossining NY, US
John Ulrich Knickerbocker - Monroe NY, US
Cornelia Kang-I Tsang - Mohegan Lake NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 23/538
US Classification:

257691, 257E23169, 257774, 257E23021, 385 14
Abstract:

An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

Integrated Module For Data Processing System
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US Patent:

7799613, Sep 21, 2010
Filed:

Aug 18, 2009
Appl. No.:

12/543144
Inventors:

Bing Dang - Ossining NY, US
John U. Knickerbocker - Monroe NY, US
Cornelia K. Tsang - Mogegan Lake NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/98
US Classification:

438121, 438108, 438109, 257691, 257E21506, 257E21705
Abstract:

An apparatus for an integrated module. A silicon carrier with through-silicon vias has a plurality of die connected to a top side of the silicon carrier. In addition, a substrate is connected to a bottom side of the silicon carrier. The substrate is coupled to the plurality of die via the through-silicon vias.

3-D Ics With Microfluidic Interconnects And Methods Of Constructing Same
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US Patent:

7928563, Apr 19, 2011
Filed:

May 28, 2008
Appl. No.:

12/128542
Inventors:

Muhannad S. Bakir - Atlanta GA, US
Deepak Sekar - Atlanta GA, US
Bing Dang - Atlanta GA, US
Calvin King, Jr. - Atlanta GA, US
James D. Meindl - Marietta GA, US
Assignee:

Georgia Tech Research Corporation - Atlanta GA
International Classification:

H01L 23/34
US Classification:

257713, 257686, 257714, 257715, 438109, 438122
Abstract:

Three dimensional integrated circuits with microfluidic interconnects and methods of constructing same are provided. According to some embodiments, and microfluidic integrated circuit system can comprise a plurality of semiconductor die wafers each having a top and bottom exterior surface. The semiconductor die wafers can form a stack of die wafers. The die wafers can comprise one or more channels formed through the die wafers. The channels can extend generally between top and bottom exterior surfaces of the semiconductor die wafers. A plurality of micro-pipes can be disposed between adjacent semiconductor die wafers in the stack. The micro-pipes can enable the channels to be in fluid communication with each other. A barrier layer can be disposed within at least one of the channels and the micro-pipes. The barrier layer can be adapted to prevent a coolant flowing through the at least one of the channels and the micro-pipes from leeching into the channels and micro-pipes.

Techniques For Forming Solder Bump Interconnects
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US Patent:

8148255, Apr 3, 2012
Filed:

Sep 18, 2007
Appl. No.:

11/856831
Inventors:

Bing Dang - Chappaqua NY, US
Peter A. Gruber - Mohegan Lake NY, US
Luc Guerin - Quebec, CA
Chirag S. Patel - Peerkskill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01L 21/44
US Classification:

438613, 438106, 438615, 438616, 257E21575, 257E2301
Abstract:

Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Silicon Carrier Optoelectronic Packaging
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US Patent:

8290008, Oct 16, 2012
Filed:

Aug 20, 2009
Appl. No.:

12/544696
Inventors:

Paul S. Andry - Yorktown Heights NY, US
Russell A. Budd - Yorktown Heights NY, US
Bing Dang - Yorktown Heights NY, US
David Danovitch - Bromont, CA
Benjamin V. Fasano - Yorktown Heights NY, US
Paul Fortier - Bromont, CA
Luc Guerin - Bromont, CA
Frank R. Libsch - Yorktown Heights NY, US
Sylvain Ouimet - Bromont, CA
Chirag S. Patel - Yorktown Heights NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

H01S 5/022
H01S 5/024
US Classification:

372 36, 372 34, 372 5012, 372 50124, 372 5023, 257690
Abstract:

An optoelectronic (OE) package or system and method for fabrication is disclosed which includes a silicon layer with wiring. The silicon layer has an optical via for allowing light to pass therethrough. An optical coupling layer is bonded to the silicon layer, and the optical coupling layer includes a plurality of microlenses for focusing and or collimating the light through the optical via. A plurality of OE elements are coupled to the silicon layer and electrically communicating with the wiring. At least one of the OE elements positioned in optical alignment with the optical via for receiving the light. A carrier is interposed between electrical interconnect elements. The carrier is positioned between the wiring of the silicon layer and a circuit board and the carrier is electrically connecting first interconnect elements connected to the wiring of the silicon layer and second interconnect elements connected to the circuit board.

Techniques For Forming Solder Bump Interconnects
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US Patent:

8328156, Dec 11, 2012
Filed:

Feb 13, 2012
Appl. No.:

13/371840
Inventors:

Bing Dang - Chappaqua NY, US
Peter A. Gruber - Mohegan Lake NY, US
Luc Guerin - Quebec, CA
Chirag S. Patel - Peekskill NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B28B 7/22
E04G 11/50
US Classification:

249 60, 249117, 257E21586
Abstract:

Interconnects are formed on attachment points of a wafer by performing several steps. A plurality of cavities having a predetermined shape is formed in a semiconductor substrate. These cavities are then filled with an interconnect material to form the interconnects. The interconnects are subsequently attached to the attachment points of the wafer.

Process For Mapping Formic Acid Distribution
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US Patent:

8342385, Jan 1, 2013
Filed:

Apr 18, 2011
Appl. No.:

13/089074
Inventors:

Bing Dang - Armonk NY, US
Raymond R. Horton - Dover Plains NY, US
Robert J. Polastre - Armonk NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B23K 31/02
B23K 35/38
US Classification:

228220, 228223, 228205, 228103, 438612, 438613
Abstract:

A transfer process for bonding a solderable device to a solderable firsl substrate having a first oxidized surface comprises placing the solderable device proximate to the first substrate in a reducing chamber, where the first surface cannot be visually observed. We place a second substrate having a second oxidized surface in the chamber in a way to visually observe the second surface. Selecting the first substrate and the second substrate so that the reduction of the second surface correlates with the reduction of the first surface provides an indication of the degree of reduction of the first surface. Introducing a reducing agent into the chamber under reducing conditions reduces the surfaces which we track by irradiating and observing the second surface; evaluate any change in the second surface during irradiation and correlate the change with first surface reduction. When sufficiently reduced, we solder the first substrate to the device.

Handler Attachment For Integrated Circuit Fabrication
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US Patent:

8388782, Mar 5, 2013
Filed:

May 27, 2010
Appl. No.:

12/788832
Inventors:

Paul S. Andry - Yorktown Heights NY, US
Bing Dang - Chappaqua NY, US
John Knickerbocker - Yorktown Heights NY, US
Peter J. Sorce - Poughkeepsie NY, US
Robert E. Trzcinski - Rhinebeck NY, US
Cornelia K. Tsang - Mohegan Lake NY, US
Assignee:

International Business Machines Corporation - Armonk NY
International Classification:

B32B 38/10
B32B 37/12
US Classification:

156 64, 156247, 156712, 156930, 438 14
Abstract:

A method for attaching a handler to a wafer, the wafer comprising an integrated circuit (IC), includes forming a layer of an adhesive on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280 C. ; and adhering a handler to the wafer using the layer of adhesive. A system for attaching a handler to a wafer, the wafer comprising IC, includes a layer of an adhesive located on the wafer, the adhesive comprising a polyimide-based polymer configured to withstand processing at a temperature of over about 280 C. ; and a handler adhered to the wafer using the layer of adhesive.