Bernd Schafferer

US Patent:

6774823, Aug 10, 2004

Filed:

Jan 22, 2003

Appl. No.:

10/349204

Inventors:

Bernd Schafferer - Gloucester MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H03M 700

US Classification:

341 61, 341 50

Abstract:

A method and apparatus for synchronizing actions of two circuits or two parts of one circuit where each circuit utilizes a different clock signal. More than one clock signal are derived from a master clock signal and run at the same frequency but have an unknown or variable phase difference. The invention solves the problem of coupling two clocked circuits where synchronization is required to properly read or sample a signal from a data line connecting the two circuits. An error window is defined during which sampling is suppressed, for example to avoid sampling during data transitions. The method of apparatus involves time shifting a pseudo-signal to generate two time-shifted signals and then defining the error window as the time during which the two time-shifted signals differ from one another.

US Patent:

6798251, Sep 28, 2004

Filed:

Aug 13, 2002

Appl. No.:

10/217681

Inventors:

Bernd Schafferer - Gloucester MA

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G01R 1900

US Classification:

327 52, 327 65, 327 71, 330258, 330261

Abstract:

Described is a differential clock receiver comprising a converter, a differential input stage, and a differential output stage. The converter converts a control signal indicative of a timing relationship into a DC offset signal. The differential input stage receives a differential clock signal and the DC offset signal. The differential input stage generates an intermediary differential signal from the differential clock. The intermediary differential signal has a DC offset resulting from the DC offset signal. The differential output stage receives the intermediary differential signal and generates at least two output signals from the intermediary differential signal. The output signals have a timing relationship determined by the DC offset of the intermediary differential signal.

US Patent:

6842132, Jan 11, 2005

Filed:

Jan 24, 2003

Appl. No.:

10/351470

Inventors:

Bernd Schafferer - Gloucester MA, US

Assignee:

Analog Devices, inc. - Norwood MA

International Classification:

H03M 100
H03M 166

US Classification:

341144, 341136

Abstract:

Methods and devices for code independent switching in signal processing circuit such as a digital-to-analog converter (DAC) are described, which provide code independent switching activity. A steering cell receives a digital data input signal that is defined at data intervals, and produces multiple representative analog output signals. For each data interval, each analog output signal depends only on the present state of the digital data input signal, independently of any previous state of the digital data input signal. In addition, the signal processing circuit apart from the analog output signals is substantially free of data dependent disturbances.

US Patent:

7796971, Sep 14, 2010

Filed:

Mar 15, 2007

Appl. No.:

11/686620

Inventors:

Yunchu Li - Andover MA, US
Bernd Schafferer - Gloucester MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04B 1/16
H04B 15/00
H03M 1/66

US Classification:

455334, 455333, 455313, 4551891

Abstract:

An electronic chip has a data input for receiving an input digital data signal with a data frequency, a plurality of switches, and a logic circuit operatively coupled with both the plurality of switches and the data input. The logic circuit controls the switches to be in one of a DAC mode or a mixer mode. The DAC mode causes the switches to convert the input digital data signal into a DAC analog signal having about the data frequency. The mixer mode, however, causes the switches to convert the input digital data signal into a mixed analog signal having a mixer frequency that is higher than the data frequency.

US Patent:

7933315, Apr 26, 2011

Filed:

Aug 15, 2006

Appl. No.:

11/504270

Inventors:

Yunchu Li - Andover MA, US
Gil Engel - Lexington MA, US
Bernd Schafferer - Wilmington MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

H04B 1/00

US Classification:

375150, 375347, 375349

Abstract:

A method for generating a data signal for synchronizing one or more electrically coupled digital receivers is disclosed. A data signal having a data rate is modulated with a pseudo-noise (PN) code having a data rate greater than the data rate of the data signal. The modulated data signal is demodulated by a receiver using the PN code. A correlation value is generated and is compared to a predetermined value to indicate phase synchronization. If the receiver is in phase synchronization with the transmitter, the received demodulated data signal is passed.

US Patent:

8031098, Oct 4, 2011

Filed:

Jan 19, 2010

Appl. No.:

12/689874

Inventors:

Christian Ebner - München, DE
Jipeng Li - Windham NH, US
Bernd Schafferer - Gloucester MA, US

Assignee:

National Semiconductor Corporation - Santa Clara CA

International Classification:

H03M 1/72

US Classification:

341146, 341144

Abstract:

In one embodiment, digital-to-analog converter (DAC) circuit includes dual DAC units employing pseudo-return-to-zero DAC operations to reduce inter-symbol interference. Moreover, each DAC unit is implemented using complementary MOS transistors to improve conversion performance. In another embodiment, a DAC calibration scheme performs background calibration of an array of DAC circuits in continuous time using a reference DAC circuit and a spare DAC circuit. Calibration (also referred to as “trimming”) of the DAC circuit using the calibration scheme of the present invention ensures that the DAC operates with high linearity over process variations. In one embodiment, the DAC circuit and the DAC calibration scheme are applied as the feedback DAC in a continuous-time sigma-delta (CT-ΣΔ) analog-to-digital converter to realize high performance and high precision analog-to-digital conversions.

US Patent:

20040032356, Feb 19, 2004

Filed:

Aug 13, 2002

Appl. No.:

10/217842

Inventors:

Bernd Schafferer - Gloucester MA, US

International Classification:

H03M001/66

US Classification:

341/144000, 341/136000

Abstract:

A system and method are provided for controlling the on/off timing relationship between two transistors in a differential that are connected at a tail node to a common current generator. The on/off timing relationship is controlled by on/off signals that control the state of the transistors such that one transistor turns one while the other is turning off. An overlap signal is derived from the tail node excursion and is indicative of whether the on/off signals are overlapping too much or too little. A control signal is generated based on the overlap signal. The timing of driver signals used to derive the on/off signals is adjusted based on the control signal. When more overlap is needed, the timing of the driver signals is adjusted such that there is more overlap of the derived on/off signals. When less overlap is needed, the timing of the driver signals is adjusted such that there is less overlap of the derived on/off signals. An embodiment that adjusts the voltage of the on/off signals to control the on/off timing is also disclosed.

US Patent:

20180241311, Aug 23, 2018

Filed:

Jul 1, 2016

Appl. No.:

15/751798

Inventors:

- Amesbury MA, US
Bernd SCHAFFERER - Amesbury MA, US

Assignee:

S9estre, LLC - Amesbury MA

International Classification:

H02M 3/158
H02M 1/088

Abstract:

Methods and devices for power conversion. High frequency electromagnetic waves traveling in coupled transmission lines and their reflective properties are used to perform the power conversion. The use of high frequency operation allows for physically small transmission lines. The high operating frequencies also allow for small filter capacitors at the outputs of the power converter and hence allowing for fast response times in load changes or fast signal changes in case of a gate driver. The transmission lines can be implemented on the printed circuit board, laminate or even on chip. In case of a step up converter the switching elements are not subjected to the higher output voltage levels of the power converter and can therefore be implemented in a lower voltage process technology. Further, embodiments with and without galvanic isolation are described and physical embodiments to reduce undesired electromagnetic emissions are disclosed.