Basem A Ayash

US Patent:

55091393, Apr 16, 1996

Filed:

Mar 22, 1993

Appl. No.:

8/034300

Inventors:

Basem A. Ayash - Houston TX
Gary W. Thome - Tomball TX

Assignee:

Compaq Computer Corp. - Houston TX

International Classification:

G06F 1202

US Classification:

395869

Abstract:

A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

US Patent:

58571167, Jan 5, 1999

Filed:

Aug 26, 1997

Appl. No.:

8/918838

Inventors:

Basem Abu Ayash - Houston TX
Gary W. Thome - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1202

US Classification:

395869

Abstract:

A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.

US Patent:

56642253, Sep 2, 1997

Filed:

Oct 27, 1995

Appl. No.:

8/524799

Inventors:

Basem Abu Ayash - Houston TX
Gary W. Thome - Tomball TX

Assignee:

Compaq Computer Corporation - Houston TX

International Classification:

G06F 1202

US Classification:

395869

Abstract:

A system management mode address correction system for a computer provides correct address values on the address bus when the computer is in system management mode. Conventionally, bit 20 of the microprocessor's address outputs may be masked by asserting the FORCE A20 signal. The computer system also operates in a system management mode, which requires all of the address bits to be available for proper access to the system management interrupt vector. When the computer is in system management mode, the computer's microprocessor asserts a system management interrupt active (SMIACT*) signal. This signal is provided to a circuit which also receives the FORCE A20 signal. While the SMIACT signal is deactivated, the control circuit provides the true FORCE A20 signal to the computer system. When an SMI occurs, the SMIACT signal is activated and the FORCE A20 signal is disabled. As a result, the address generated by the microprocessor is asserted on the address bus.