Bart R Mcdaniel

US Patent:

6400189, Jun 4, 2002

Filed:

Dec 14, 1999

Appl. No.:

09/460743

Inventors:

Bart R. McDaniel - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03B 100

US Classification:

327108, 327390, 327103, 327333, 326 83, 326 88

Abstract:

A buffer circuit includes an amplifier, a pass gate circuit and a level shifter. The pass gate circuit communicates an input signal to the amplifiers and includes a terminal to control the communication. A level shifter furnishes a control signal to the terminal of the pass gate circuit and regulates the control signal based on a magnitude of the input signal.

US Patent:

6425086, Jul 23, 2002

Filed:

Apr 30, 1999

Appl. No.:

09/302560

Inventors:

Lawrence T. Clark - Phoenix AZ
Bart McDaniel - Phoenix AZ
Jay Heeb - Phoenix AZ
Tom J. Adelmeyer - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

713322

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

US Patent:

6519707, Feb 11, 2003

Filed:

Sep 10, 2001

Appl. No.:

09/951109

Inventors:

Lawrence T. Clark - Phoenix AZ
Bart McDaniel - Phoenix AZ
Jay Heeb - Phoenix AZ
Tom J. Adelmeyer - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 132

US Classification:

713322

Abstract:

Briefly, in accordance with one embodiment of the invention, a system includes: a processor, a voltage regulator, and a memory. The voltage regulator is coupled to the processor to adjust the operating voltage of the processor. The memory is coupled to the processor by a memory bus. The memory has stored on it processor instructions that, when executed by the processor, result in modification of the operating frequency of the processor and result in adjustment of the operating voltage of the processor, based, at least in part, on dynamic changes in the processing load of the processor.

US Patent:

6545627, Apr 8, 2003

Filed:

Dec 19, 2001

Appl. No.:

10/033954

Inventors:

Yueming He - Chandler AZ
Bart R. McDaniel - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 112

US Classification:

341155, 341120, 341150, 341172

Abstract:

Briefly, in accordance with an embodiment of the invention, a method and circuit to perform an analog-to-digital conversion is provided. The method may include generating and storing a combined charge which is generated by combining an input charge and a reference charge.

US Patent:

6891488, May 10, 2005

Filed:

Oct 30, 2003

Appl. No.:

10/696946

Inventors:

Bart R. McDaniel - Phoenix AZ, US
Malcolm H. Smith - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M003/00

US Classification:

341143, 341144, 341155

Abstract:

An N-order sigma-delta analog-to-digital converter (ADC) system having multilevel quantized feedback. A multilevel quantized feedback stage incorporates a multibit, current-mode digital-to-analog converter (DAC). In one embodiment, reference current sources for the DAC may comprise a plurality of floating-gate MOS transistors so that analog nonvolatile precision linearity trimming of the feedback DAC may be accomplished. Calibration of the DAC may be performed at a relatively low refresh rate, for example, only at instances when the sigma-delta ADC system is activated.

US Patent:

7233776, Jun 19, 2007

Filed:

Jun 29, 2004

Appl. No.:

10/879544

Inventors:

Kevin W. Glass - Scottsdale AZ, US
Bart R. McDaniel - Phoenix AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04B 1/44

US Classification:

455 78, 455 633, 455561, 4555621, 363 16, 363 49, 363 218

Abstract:

According to one embodiment a microelectromechanical (MEMS) switch is disclosed. The MEMS switch includes a pulse generator to provide a low voltage source, a transformer coupled to the pulse generator to boost a voltage received from the pulse generator and a switch component coupled to the pulse generator. The switch component includes an actuation capacitor to store charge associated with the voltage received from the transformer.

US Patent:

62559796, Jul 3, 2001

Filed:

Feb 24, 1999

Appl. No.:

9/258116

Inventors:

David R. Allee - Phoenix AZ
Bart R. McDaniel - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 136

US Classification:

341159

Abstract:

An analog-to-digital converter (ADC) is provided. The analog-to-digital converter includes a plurality of differential comparators. For each of the plurality of differential comparators the ADC receives differential input signals and differential reference signals and generates an output signal. The ADC also includes a self-calibration circuit to receive from each of the plurality of differential comparators the output signal. In response to the output signal, the self-calibration circuit generates a self-calibration signal. The ADC further includes an adjustable reference signal generator to provide the differential reference signals based on the self-calibration signal.

US Patent:

53010973, Apr 5, 1994

Filed:

Jun 10, 1992

Appl. No.:

7/896195

Inventors:

Bart R. McDaniel - Phoenix AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H02M 725

US Classification:

363 60

Abstract:

A multiple staged charge pump network with staggered clock phases for pumping a first voltage to a second voltage with high current capability. The charge pump includes multiple serial charge pumps connected in parallel, multi-phase clocks, input voltage and output voltage connectors. The multiple serial charge pumps have in each series a plurality of diode-connected n-channel MOSFETs. The first n-channel MOSFET in each series is coupled to the input voltage connector, while the rest of the n-channel MOSFETs are coupled to a pumping capacitor at their diode-connected gates. The clocks are coupled to the multiple serial charge pumps for generating a plurality of phases of clocks with each phase of the clocks being applied to the alternating n-channel MOSFETs in a series such that adjoining n-channel MOSFETs are not driven by the same phase of clock. The input voltage connector is coupled to the first n-channel MOSFET in each series of the multiple serial charge pump for providing an input voltage. The output voltage connector is coupled to the last n-channel MOSFET in each series of the multiple serial charge pump for generating an output voltage after the input voltage is switched-regulated through the multiple serial charge pump.