Bart J Martinec

US Patent:

8004319, Aug 23, 2011

Filed:

Nov 30, 2009

Appl. No.:

12/627276

Inventors:

Bhoodev Kumar - Austin TX, US
Bart J. Martinec - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

H03K 21/00

US Classification:

327115, 327117, 377 47

Abstract:

In one or more embodiments, a programmable clock divider (PCD) can receive an input clock signal and a programmable number, and the PCD can produce a divided clock signal based on the programmable number. First and second circuits can compare first and second numbers, respectively, with a count value from a counter to generate first and second signals, respectively. A multiplexer can receive the first and second signals at inputs and can receive the clock signal at a selection input. The multiplexer can output an output signal, as a divided clock signal, based on the clock signal, the first signal, and the second signal, where the output signal transitions from a first value to a second value on at least one of a first edge of the first clock signal to output the first signal and a second edge of the first clock signal to output the second signal.

US Patent:

20070226561, Sep 27, 2007

Filed:

Mar 23, 2006

Appl. No.:

11/388154

Inventors:

Milind Padhye - Austin TX, US
Darrell Carder - Dripping Springs TX, US
Bhoodev Kumar - Austin TX, US
Bart Martinec - Austin TX, US

Assignee:

Freescale Semiconductor, Inc. - Austin TX

International Classification:

G01R 31/28

US Classification:

714726000

Abstract:

A circuit device having data retention latches utilizes a test interface and system test controller to control one or more components of the circuit device to ensure proper conditions for testing the data retention latches. The data retention latches each include a scan component that is part of a scan chain, a first latching component that is powered in a first voltage domain and a second latching component that is powered in a second voltage domain, where one of the voltage domains can be effectively shut down when the circuit device is placed in a low-voltage mode. The system test controller can control a scan controller used to scan test data in and out of the scan chain. The system test controller further can control a power controller used to manage a power down sequence and a power up sequence so as to ensure that the data retention latches are not placed in spurious states.