Barry B Mead

US Patent:

45933936, Jun 3, 1986

Filed:

Feb 6, 1984

Appl. No.:

6/577097

Inventors:

Barry B. Mead - Mesa AZ
Gerald V. Piosenka - Scottsdale AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1110

US Classification:

371 37

Abstract:

Method and apparatus for operating a CRC in a parallel, quasi parallel or serial fashion. The device allows all the bits in a word to be read and loaded into the cyclic redundancy checker (CRC) register in one clock cycle putting it in sync with the rest of the system. The CRC consists of a set of logic gates for converting a parallel input signal to a converted parallel input signal that is the equivalent of the conversion performed on the serial data input into the prior art cyclic redundancy checkers. The bits of the converted parallel input signal are then combined in another set of logic gates to provide the CRC output.

US Patent:

46111832, Sep 9, 1986

Filed:

Apr 30, 1984

Appl. No.:

6/605366

Inventors:

Gerald V. Piosenka - Scottsdale AZ
Barry B. Mead - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H03B 2900

US Classification:

331 78

Abstract:

An apparatus and method is disclosed that provides a random data generator that is less susceptible to error sources resulting from negative feedback biasing. This invention utilizes a shift register and a multiplexer, controlled by the shift register, to provide the feedback to an amplifier. This improves the correlation between the present data output bit and the following bit.

US Patent:

45981701, Jul 1, 1986

Filed:

May 17, 1984

Appl. No.:

6/611560

Inventors:

Gerald V. Piosenka - Scottsdale AZ
Barry B. Mead - Mesa AZ

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

H04L 900

US Classification:

178 2208

Abstract:

An apparatus and method is disclosed for the protection of computer programs through the use of the principles of conditional inversion and permutation. These security features are designed as part of the chip in a fashion to minimize the changes required to any existing microprocessor design and to be transparent to firmware execution. The programs are first encrypted by permutation which reorders the lines according to an allocated scheme and then conditionally inverted through a set of dual input exclusive OR gates. The reordering of lines in the permutator and the conditional inversion in the inverter are accomplished through the use of variables some of which are permanently prestored in the microprocessor and some of which are entered by the programmer.