Search

Balaji Narasimham

age ~43

from Aliso Viejo, CA

Get Report
Also known as:
  • Bala Narasimham
  • Narasimham Balaji
  • Balaji M
Phone and address:
22 Nutcracker Ln, Laguna Beach, CA 92656
Related to:
Connected to:

Balaji Narasimham Phones & Addresses

  • 22 Nutcracker Ln, Aliso Viejo, CA 92656
  • Laguna Beach, CA
  • Santa Ana, CA
  • 2310 Elliott Ave, Nashville, TN 37204 • 615 730-7144
  • 2310 Elliott Ave APT 523, Nashville, TN 37204 • 615 730-7144
  • 2901 Euclid Ave, Cleveland, OH 44115
  • Streetsboro, OH

Work

  • Company:
    Broadcom
    Oct 2008
  • Position:
    Senior staff reliability scientist

Education

  • Degree:
    Ph.D.
  • School / High School:
    Vanderbilt University
    2006 to 2008
  • Specialities:
    Electrical Engineering

Skills

Semiconductors • Circuit Design • Soft Errors • Reliability

Industries

Semiconductors

Us Patents

  • Hysteresis-Based Latch Design For Improved Soft Error Rate With Low Area/Performance Overhead

    view source
  • US Patent:
    20130234753, Sep 12, 2013
  • Filed:
    May 23, 2012
  • Appl. No.:
    13/478760
  • Inventors:
    Karthik Chandrasekharan - Scottsdale AZ, US
    Balaji Narasimham - Santa Ana CA, US
    Gregory Djaja - Phoenix AZ, US
  • Assignee:
    BROADCOM CORPORATION - Irvine CA
  • International Classification:
    H03K 19/003
  • US Classification:
    326 9
  • Abstract:
    A hysteresis-based logic element design for improved soft error rate with low area/performance overhead. In one embodiment, a hysteresis inverter block including one or more pairs of inverters can be coupled to a logic element to adjust a switching threshold of the logic element.

  • Clocked Miller Latch Design For Improved Soft Error Rate

    view source
  • US Patent:
    20190319622, Oct 17, 2019
  • Filed:
    Apr 13, 2018
  • Appl. No.:
    15/952609
  • Inventors:
    - Singapore, SG
    Balaji Narasimham - Aliso Viejo CA, US
  • International Classification:
    H03K 19/003
    H03K 3/037
    G11C 11/419
    G11C 11/412
  • Abstract:
    Systems, circuits, and chips for hardening a latch/flip-flop circuit against soft errors caused by alpha and neutron radiation are provided. As an example, a latch/flip-flop circuit including a switch to selectively couple a capacitor to first and second storage nodes during a hold phase is disclosed.

Resumes

Balaji Narasimham Photo 1

Staff Reliability Scientist At Broadcom

view source
Position:
Senior Staff Reliability Scientist at Broadcom
Location:
Orange County, California Area
Industry:
Semiconductors
Work:
Broadcom since Oct 2008
Senior Staff Reliability Scientist
Vanderbilt University Aug 2003 - Oct 2008
Graduate Research Assistant
IBM T. J. Watson Research Center May 2006 - Aug 2006
Research Intern
Intel May 2005 - Aug 2005
Technical Intern
Education:
Vanderbilt University 2006 - 2008
Ph.D., Electrical Engineering Vanderbilt University 2003 - 2005
M.S., Electrical Engineering University of Madras 1999 - 2003
B.E., Electrical and Electronics Engineering Padma Seshadri Bala Bhavan 1997 - 1999
High School
Skills:
Semiconductors
Circuit Design
Soft Errors
Reliability
Get Report for Balaji Narasimham from Aliso Viejo, CA, age ~43
Control profile