Augusto Felipe Gallegos Alcantara

US Patent:

7460545, Dec 2, 2008

Filed:

Jun 14, 2004

Appl. No.:

10/867199

Inventors:

Juan-Carlos Calderon - Fremont CA, US
Soowan Suh - San Ramon CA, US
Jing Ling - Fremont CA, US
Jean-Michel Caia - San Francisco CA, US
Augusto Alcantara - Fremont CA, US
Alejandro Lenero Beracoechea - Dublin CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 12/28

US Classification:

3703957, 370321, 370347, 370382, 370379, 711 5

Abstract:

A method and apparatus for managing memory for time division multiplexed high speed data traffic is provided. The method and apparatus utilize an interleaving approach in association with multiple memory banks, such as within SDRAM, to perform highly efficient data reading and writing. The design issues a first command or access command, such as a read command or write command to one memory bank, followed by an active command to a second memory bank, enabling efficient reading and writing in a multiple data flow environment, such as a SONET/SDH virtual concatenation environment using differential delay compensation.