Arvind Sundararajan

US Patent:

7571395, Aug 4, 2009

Filed:

Aug 3, 2005

Appl. No.:

11/196174

Inventors:

Shay Ping Seng - San Jose CA, US
Arvind Sundararajan - Palo Alto CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 1, 716 16, 716 17, 326 38, 326 39, 326 41

Abstract:

Generation of a circuit design using a command language. The various approaches include generating in a memory arrangement respective instances of design blocks in response to user-entered commands that specify creation of the instances. Matrix-relative positions of the instances of design blocks are established in the memory arrangement in response to at least one user-entered command that specifies respective matrix positions of the instances. Representative connections between the instances are generated in the memory arrangement in response to a user-entered command having no specification of the connections.

US Patent:

7643688, Jan 5, 2010

Filed:

Oct 10, 2003

Appl. No.:

10/683322

Inventors:

Ramin Samadani - Menlo Park CA, US
Arvind Sundararajan - Palo Alto CA, US
Amir Said - Cupertino CA, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06K 9/36
G06K 9/40

US Classification:

382232, 382268

Abstract:

Systems and methods of reducing artifacts in compressed images are described. In one aspect, spatially-shifted forward transforms of the input image are computed to generate respective sets of forward transform coefficients. Nonlinear transforms are applied to the forward transform coefficients of each set. Inverse transforms of the sets of nonlinearly transformed forward transform coefficients are computed to generate respective intermediate images. Respective measures of local spatial intensity variability are computed for pixels of each of the intermediate images. An output image is computed with pixel values computed based at least in part on the computed measures of local spatial intensity variability.

US Patent:

7933900, Apr 26, 2011

Filed:

Oct 23, 2005

Appl. No.:

11/257282

Inventors:

Bindu Reddy - San Francisco CA, US
Jonathan Brunsman - San Jose CA, US
Ning Mosberger - Fremont CA, US
Gaurav Ravindra Bhaya - Sunnyvale CA, US
Sarah Sirajuddin - Mountain View CA, US
David Kale - Palo Alto CA, US
Jennifer L. Kozenski - Sunnyvale CA, US
Arvind Sundararajan - San Francisco CA, US
Puneet Agarwal - Mountain View CA, US

Assignee:

Google Inc. - Mountain View CA

International Classification:

G06F 7/00
G06F 17/30

US Classification:

707732, 707706, 707754

Abstract:

A user can refine a search over structured data by specifying that a label or an attribute value be used to further filter the results of a query.

US Patent:

8015537, Sep 6, 2011

Filed:

May 19, 2009

Appl. No.:

12/468640

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716134, 716108, 716113, 716106, 716100

Abstract:

A computer-implemented method of automatic rate realization for implementing a circuit design within a programmable integrated circuit can include comparing data rates of clock domains of the circuit design with frequencies of available clock sources of the circuit design and determining which clock domains have data rates that match frequencies of clock sources. For each clock domain that has a data rate matching a frequency of a clock source, loads of the clock domain can be clocked using a multiple synchronous clock technique with the matching clock source. For each clock domain having a data rate that does not match a frequency of a clock source, loads of the clock domain can be clocked using a clock enable technique. The circuit design specifying the clock circuitry for each clock domain can be output.

US Patent:

8024678, Sep 20, 2011

Filed:

Apr 1, 2009

Appl. No.:

12/416333

Inventors:

Bradley L. Taylor - Santa Cruz CA, US
Arvind Sundararajan - Sunnyvale CA, US
Shay Ping Seng - San Jose CA, US
L. James Hwang - Portola Valley CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716100, 716104, 716126, 716128, 708170, 708490, 708495, 712200, 712220, 712221, 712222, 712223

Abstract:

An interface to a dynamically configurable arithmetic unit can include data alignment modules, where each data alignment module receives input variables being associated with one or more arithmetic expressions. The interface can include multiplexers coupled to the data alignment modules, wherein a data alignment module has outputs coupled to a first multiplexer. The first multiplexer can have a selection line and an output coupled to an input port of the dynamically configurable arithmetic unit. The interface can include a second multiplexer having input instructions and the selection line, where each instruction is associated with one of the arithmetic expressions and has an operation to be performed by the dynamically configurable arithmetic unit. The second multiplexer is configurable to provide selected ones of the input instructions to the dynamically configurable arithmetic unit through an output of the second multiplexer responsive to the selection line.

US Patent:

8042079, Oct 18, 2011

Filed:

May 19, 2009

Appl. No.:

12/468764

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Haibing Ma - Superior CO, US
Andrew Dow - Edinburgh, GB
Singh Vinay Jitendra - Fremont CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716106, 716121, 717104, 717109, 712225

Abstract:

Design synchronization for a High-Level Modeling System (“HLMS”) of an integrated circuit device (“IC”) is described. In a method for generating a netlist, a description of a first circuit block of a user design is input to a programmed computer system programmed with a computer-aided modeling system. The description includes output port information of the first circuit block and synchronization signal information. The computer-aided modeling system selects a circuit core for the first circuit block responsive to output port information and the synchronization signal information, the circuit core including port metadata. The computer-aided modeling system selects at least one macro responsive to the port metadata for generation of the netlist. The macro is for rate synchronized coupling of the first circuit block to a second circuit block of the user design. The computer-aided modeling system outputs the netlist including the macro.

US Patent:

8219958, Jul 10, 2012

Filed:

Mar 9, 2010

Appl. No.:

12/720563

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50
G06F 9/455
G06F 11/22

US Classification:

716121, 716132, 716136

Abstract:

Within a system comprising a processor and a memory, a method of creating evaluation hardware within an integrated circuit can include automatically inserting, by the processor, a disable circuit block into a circuit design. The method can also include automatically selecting a location within the circuit design to insert the disable circuit block, and/or inserting an unlock circuit block into the circuit design, wherein responsive to receiving an unlock code, the unlock circuit block overrides the disable circuit block. The method also can include storing, within the memory, the circuit design comprising the disable circuit block.

US Patent:

8417965, Apr 9, 2013

Filed:

Apr 7, 2010

Appl. No.:

12/755760

Inventors:

Arvind Sundararajan - Sunnyvale CA, US
Chi Bun Chan - San Jose CA, US
Nabeel Shirazi - Saratoga CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 11/30
G06F 12/14
G06F 7/04
G06F 17/30
G06F 9/445
H04L 29/06
H04L 9/00
H04L 9/30
H04K 1/00
H04N 7/16

US Classification:

713189, 713150, 713187, 380 30, 726 26, 717174

Abstract:

An embodiment of the present invention provides a method and circuit for secure definition and integration of a core into a circuit design without exposing the core. In one embodiment, a core development package is obtained. The core development package includes an encrypted core and a decryption key of the encrypted core. The decryption key is encrypted with an asymmetric cipher. The encrypted core is transmitted from the design tool to a trusted platform module. The decryption key is decrypted with a private key of the asymmetric cipher. The encrypted core is decrypted within the trusted platform module. One or more design tool operations are performed using the decrypted core.