Arthur R Wang

US Patent:

6347054, Feb 12, 2002

Filed:

Feb 1, 2000

Appl. No.:

09/496293

Inventors:

Arthur Arthur Wang - Saratoga CA

Assignee:

Hyundai Electronics America - San Jose CA

International Classification:

G11C 1604

US Classification:

36518529, 36518518, 36518526

Abstract:

A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6. 5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8. 0 volts.

US Patent:

6366499, Apr 2, 2002

Filed:

Oct 10, 2000

Appl. No.:

09/689026

Inventors:

Arthur Arthur Wang - Saratoga CA
Ming Kwan - San Leandro CA

Assignee:

Hyundai Electronics America - San Jose CA

International Classification:

G11C 1604

US Classification:

36518528, 36518518

Abstract:

A method of programming an electrically programmable memory cell which cell includes a transistor formed in a semiconductor substrate of first conductivity type having a surface a first well region of second conductivity type is disposed in the substrate adjacent the surface thereof. A second well region of first conductivity type is disposed in the first well region adjacent the surface. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes raising the control gate to a first selected potential no greater than 9. 0 volts, raising the drain to a potential to no more than 5. 0 volts, coupling the source region to ground potential, coupling the first well region of second conductivity type to ground potential, and placing the second well region at a potential below ground potential.

US Patent:

6525970, Feb 25, 2003

Filed:

Oct 12, 2001

Appl. No.:

09/976232

Inventors:

Arthur Wang - Saratoga CA
Ming Kwan - San Leandro CA

Assignee:

Hyundai Electronics America - San Jose CA

International Classification:

G11C 1604

US Classification:

36518529, 36518518, 36518526

Abstract:

A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method comprises lowering the control gate to a potential of about -9 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential of about 9 volts.

US Patent:

7172939, Feb 6, 2007

Filed:

Nov 15, 2005

Appl. No.:

11/280529

Inventors:

Kai Cheng Chou - San Jose CA, US
Harry Laun - Saratoga CA, US
Kenlin Huang - Fremont CA, US
J. C. Young - Milpitas CA, US
Arthur Wang - San Jose CA, US

Assignee:

Winbond Electronics Corporation - Hsin-Chu

International Classification:

H01L 21/336

US Classification:

438257, 438197, 257E2168, 257E21698

Abstract:

An MONOS integrated circuit device. The device has a semiconductor substrate comprising a silicon bearing material and a shallow trench isolation region formed within the substrate. A P-type well region is formed within the substrate and adjacent to the shallow trench isolation region. The first word gate comprising a first edge and a second edge. The first word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. Preferably, the second word gate comprises a first edge and a second edge. The second word gate comprises a first control gate coupled to the first edge and a second control gate coupled to the second edge. A common buried bit line is formed within the P-type well region and between the second edge of the first word gate and the first edge of the second word gate. An HDP plasma dielectric is formed overlying the common buried bitline to a height within a vicinity of a first surface of the first word gate and a second surface of the second word gate. In a preferred embodiment, the device has a planarized surface formed from a portion of the HDP plasma dielectric, the first surface, and the second surface.

US Patent:

7186658, Mar 6, 2007

Filed:

May 24, 2004

Appl. No.:

10/854755

Inventors:

Kenlin Huang - Fremont CA, US
Kaicheng Chou - San Jose CA, US
Harry Luan - Saratoga CA, US
Arthur Wang - San Jose CA, US

Assignee:

Winbond Electronics Corporation - Hsin-Chu

International Classification:

H01L 21/302
H01L 21/461

US Classification:

438706, 438734

Abstract:

A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e. g. , Cl+HBr+CF) gas combination and over etch step of (e. g. , HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

US Patent:

7408212, Aug 5, 2008

Filed:

Feb 11, 2004

Appl. No.:

10/777560

Inventors:

Harry S. Luan - Saratoga CA, US
Arthur Wang - San Jose CA, US
Kai-Cheng Chou - San Jose CA, US
Kenlin Huang - Fremont CA, US

Assignee:

Winbond Electronics Corporation

International Classification:

H01L 29/76

US Classification:

257295, 257296, 257E29338

Abstract:

An electrically programmable, non-volatile resistive memory includes an array of memory cells, a plurality of bit lines, and a plurality of word lines. Each memory cell comprises a resistive element and a Schottky diode coupled in series and having first and second terminals. Each bit line couples to the first terminal of all memory cells in a respective column of the array. Each word line couples to the second terminal of all memory cells in a respective row of the array. The resistive element for each memory cell may be formed with a film of a perovskite material (e. g. , PrCaMnO). The Schottky diode for each memory cell may be formed by a thin film of amorphous silicon. The films for the resistive element and Schottky diode for each memory cell may be stacked in a compact island at the cross point between a bit line and a word line.

US Patent:

20070126052, Jun 7, 2007

Filed:

Dec 1, 2005

Appl. No.:

11/292941

Inventors:

Harry Luan - Saratoga CA, US
J.C. Young - Milpitas CA, US
Arthur Wang - San Jose CA, US
K.C. Chou - San Jose CA, US
Kenlin Huang - Fremont CA, US

Assignee:

Winbond Electronics Corporation America - San Jose CA

International Classification:

H01L 29/792

US Classification:

257324000

Abstract:

A method of manufacturing a non-volatile semiconductor memory. The method includes forming a word gate poly layer on a substrate, wherein an upper surface of the substrate defines a plane of the substrate. The method also includes forming a first dielectric layer coupled to the word gate poly layer and patterning the word gate poly layer and the first dielectric layer to form an array of word gate structures. The method further includes forming a poly plug layer and patterning the poly plug layer to form a plurality of poly plugs surrounded in the plane of the substrate on three sides, forming a plurality of control gates, forming a second dielectric layer, planarizing the second dielectric layer using a chemical-mechanical polishing process, and depositing a metal layer to provide electrical contact to the word gate structures.

US Patent:

63301903, Dec 11, 2001

Filed:

May 27, 1997

Appl. No.:

8/863918

Inventors:

Arthur Wang - Saratoga CA
Ming Kwan - San Leandro CA

Assignee:

Hyundai Electronics America - San Jose CA

International Classification:

G11C 1604

US Classification:

36518528

Abstract:

A semiconductor structure for a flash memory has memory cells which are formed in a first conductivity type well, which in turn is formed within an opposite conductivity type well. The opposite conductivity type well is formed in the substrate. Additional regions within each of the first and opposite conductivity type wells are used to provide electrical connections to the corresponding well. This structure is particularly advantageous because it provides the ability to operate the flash memory with considerably lower operating potentials than prior art flash memories.