Arthur D Herbig

US Patent:

41557840, May 22, 1979

Filed:

Apr 8, 1977

Appl. No.:

5/785881

Inventors:

Thomas G. Mills - Carson CA
Wallace T. Anderson - Huntington Beach CA
Arthur D. Herbig - San Jose CA

Assignee:

TRW Inc. - Redondo Beach CA

International Classification:

H01L 21205
H01L 21465
H01L 2920

US Classification:

148175

Abstract:

A process for epitaxially forming a layer of gallium arsenide having a first conductivity on a substrate of gallium arsenide having a second conductivity in an enclosure having an inner liner comprised of a silicon compound, comprising decomposing arsine to form arsenic; chemically reacting a first quantity of hydrogen chloride and gallium to form gallium chloride, the gallium chloride reacting with the arsenic to form gallium arsenide on the substrate, a portion of the first quantity of hydrogen chloride remaining unreacted and tending to cause silicon contaminants from the liner to be deposited on the substrate; and providing a second quantity of hydrogen chloride into the enclosure which serves to initially etch, and hence clean, the outer surface of the substrate prior to the formation of gallium arsenide thereon, and simultaneously tends to inhibit the formation of silicon contaminants on the substrate, the second quantity and the first quantity having a preselected ratio such that the growth rate of the gallium arsenide layer on the substrate is greater than the etching rate of gallium arsenide due to the second quantity of hydrogen.

US Patent:

47881569, Nov 29, 1988

Filed:

Sep 24, 1986

Appl. No.:

6/911270

Inventors:

Edward B. Stoneham - Los Altos CA
Masahiro Omori - Palo Alto CA
Arthur D. Herbig - San Jose CA

Assignee:

Microwave Technology, Inc. - Fremont CA

International Classification:

H01L 21265
H01L 21324

US Classification:

437022

Abstract:

One embodiment of a process in accordance with our invention includes the step of forming a P type region on a semiconductor substrate. After the P type region is formed, an N type layer is epitaxially grown on the P type region. A Schottky gate is then formed on the N type epitaxial layer. A first portion of the epitaxial layer serves as a transistor source, a second portion of the epitaxial layer serves as the transistor drain, and a third portion of the epitaxial layer serves as the channel. Of importance, the P type semiconductor region helps prevent various short channel effects caused when current carriers flowing between the source and drain flow too far from the Schottky gate.