Armando Garcia

Author:

Armando Ramos Garcia

ISBN #:

8424125207

Author:

Armando Grana Garcia

ISBN #:

8460443663

Author:

Armando Grana Garcia

ISBN #:

8479250151

Address:

4271 NW South Tamiami Canal Dr APT 203, Miami, FL 33126

Phone:

305 828-5000

VIN:

KMHCU4AE6CU237829

Make:

HYUNDAI

Model:

ACCENT

Year:

2012

Address:

6713 SW 134 Ct, Miami, FL 33183

VIN:

2HNYD2H29AH503297

Make:

ACURA

Model:

MDX

Year:

2010

Address:

6713 SW 134 Ct, Kendall, FL 33183

Phone:

305 632-9932

VIN:

JN1BZ34D68M706720

Make:

NISSAN

Model:

350Z

Year:

2008

Address:

940 W 56 St, Hialeah, FL 33012

VIN:

1GKER23737J164948

Make:

GMC

Model:

Acadia

Year:

2007

Address:

221 SW 112 Ave, Miami, FL 33174

VIN:

1GCGG25UX71122273

Make:

CHEVROLET

Model:

EXPRESS CARGO

Year:

2007

Address:

10701 SW 47 St, Miami, FL 33165

VIN:

1B3HB28B37D111550

Make:

DODGE

Model:

CALIBER

Year:

2007

Address:

569 Pinecrest Dr, Miami Springs, FL 33166

VIN:

1NXBR32E67Z822986

Make:

TOYOTA

Model:

COROLLA

Year:

2007

Address:

5905 E 4 Ave, Hialeah, FL 33013

VIN:

1N4BA41E37C813726

Make:

NISSAN

Model:

MAXIMA

Year:

2007

US Patent:

54695422, Nov 21, 1995

Filed:

Jul 22, 1991

Appl. No.:

7/733767

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1300
G06F 1100

US Classification:

39520001

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

62020978, Mar 13, 2001

Filed:

Jan 17, 1995

Appl. No.:

8/373052

Inventors:

David James Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert Bernard Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 15173

US Classification:

709238

Abstract:

Apparatus and method for use in a multiprocessor system (10) having a plurality of processing nodes (P0-P3) each of which includes a local data processor (22a, 28a). The apparatus includes an interface (42) to a controller (14), the interface including a register (48) for storing a function received from the controller, such as a diagnostic function. The interface further includes circuitry (50) for providing the diagnostic function as a packet to an input terminal of a bit serial communication bus (40). The communication bus is threaded through each of the plurality of processing nodes and has an output terminal that terminates at the interface. Each of the nodes includes a register (54) for receiving the packet and, responsive to information conveyed thereby, for halting the local data processor and for controlling the operation of local data processor control signal lines, data signal lines, and address signal lines so as to execute the diagnostic function, such as reading data from or writing data to a specified location. The local data processor may also be reset, rebooted, restarted from a halted condition, or interrupted.

US Patent:

53275705, Jul 5, 1994

Filed:

Jul 22, 1991

Appl. No.:

7/734432

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY
Robert B. Pearson - Cold Spring NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 900

US Classification:

395800

Abstract:

A multiprocessor data processing system (10), and a method of operating same, so as to provide efficient bandwidth utilization of shared system resources (24, 26). The system includes a plurality of processor nodes, each of which includes a data processor (22a, 28a). A first step of a method buffers data written by a data processor to a first bus (23a), prior to the data being transmitted to a second bus (32). Also buffered are byte enable (BE) signals generated by the data processor in conjunction with the data written by the data processor. A next step performs a main memory (26) write operation by transmitting the buffered data to the second bus; responsive to the stored BE signals, also transmitting a control signal for indicating if a memory write is to be accomplished as a read-modify-write (RMW) type of memory operation; and transmitting the stored BE signals to the second bus. A further step couples the data, the RMW signal, and the BE signals from the second bus to a third bus (24) for reception by the main memory.

US Patent:

54106540, Apr 25, 1995

Filed:

Jul 22, 1991

Appl. No.:

7/733517

Inventors:

David J. Foster - White Plains NY
Armando Garcia - Yorktown Heights NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1502

US Classification:

395275

Abstract:

Interface circuitry for coupling to a microprocessor device. The interface circuitry includes an input for receiving address signal lines and control signal lines generated by the microprocessor device. The interface further includes an address decoder, responsive to the received address signal lines, for determining if a microprocessor-generated memory access is directed to a private memory, accessible only by the microprocessor device, or to a shared memory that is accessible by a plurality of microprocessor devices. Responsive to the address decoder, the interface circuitry provides first address signal lines and first control signal lines to the private memory in response to the microprocessor device generating a memory access to the private memory. Also responsive to the address decoder, the interface circuitry provides second address signal lines and second control signal lines for coupling to the shared memory in response to the microprocessor device generating a memory access to the shared memory. The interface circuitry further includes interrupt control circuitry, inter-processor interrupt circuitry, DMA circuitry, a serial bus interface, and also provides a plurality of miscellaneous functions for the microprocessor.