Ankur O Agrawal

Author:

Ankur Agrawal

ISBN #:

8175411848

US Patent:

8564352, Oct 22, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/538276

Inventors:

Ankur Agrawal - White Plains NY, US
John F. Bulzacchelli - Yonkers NY, US
Sergey V. Rylov - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03H 11/16

US Classification:

327237, 327231

Abstract:

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

US Patent:

8633764, Jan 21, 2014

Filed:

Jun 10, 2011

Appl. No.:

13/157957

Inventors:

Ankur Agrawal - White Plains NY, US
John F. Bulzacchelli - Yonkers NY, US
Thomas H. Toifl - Zurich, CH

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03F 3/00

US Classification:

330 11, 330258, 327336

Abstract:

An apparatus comprises an amplifier circuit comprising at least one output node and a common-mode restoration circuit capacitively coupled to the at least one output node of the amplifier circuit. The common-mode restoration circuit is configured to introduce at least one common-mode restoring signal onto the output node, wherein the at least one common-mode restoring signal transitions in correspondence with an operation interval of the amplifier circuit and thereby compensates for a common-mode voltage drop on the at least one output node of the amplifier circuit. In one example, the amplifier circuit may comprise a current-integrating amplifier circuit, and the operation interval may comprise an integration interval.

US Patent:

20130207702, Aug 15, 2013

Filed:

Jun 27, 2012

Appl. No.:

13/534241

Inventors:

John F. Bulzacchelli - Yonkers NY, US
Ankur Agrawal - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk CA

International Classification:

H03K 3/84

US Classification:

327164

Abstract:

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

US Patent:

20130207703, Aug 15, 2013

Filed:

Jun 27, 2012

Appl. No.:

13/534596

Inventors:

John F. Bulzacchelli - Yonkers NY, US
Ankur Agrawal - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/84

US Classification:

327164

Abstract:

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

US Patent:

20130207708, Aug 15, 2013

Filed:

Jun 29, 2012

Appl. No.:

13/538621

Inventors:

Ankur Agrawal - White Plains NY, US
John F. Bulzacchelli - Yonkers NY, US
Sergey V. Rylov - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 5/13

US Classification:

327237

Abstract:

A phase interpolator circuit is provided that generates an output clock signal by interpolating between phases of first and second clock signals. Interpolation is performed by detecting an edge of the first clock signal and applying a first current to charge a capacitance of an output node to a voltage level which is less than or equal to a switching threshold of a voltage comparator, and detecting an edge of the second clock signal and applying a second current to charge the capacitance of the output node to a voltage level which exceeds the switching threshold of the voltage comparator. The magnitude of the first current is varied to adjust a timing at which the capacitance of the output node is charged to a voltage level that exceeds the switching threshold of the voltage comparator and to adjust a phase of the output clock signal output from the voltage comparator.

US Patent:

20130300481, Nov 14, 2013

Filed:

Jul 22, 2013

Appl. No.:

13/947224

Inventors:

Ankur Agrawal - White Plains NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H03K 3/017

US Classification:

327175

Abstract:

Circuits and methods are provided for generating clock signals and correcting duty cycle distortion in clock signals. A circuit for generating a clock signal includes a multiplexer circuit and an edge-triggered flip-flop circuit. The multiplexer circuit selectively outputs one of a plurality of input clock signals. The edge-triggered flip-flop detects a transitioning edge of the input clock signal that is selectively output from the multiplexer circuit, and in response to the detection, samples a logic level of a received data signal, and generates a transition of an output clock signal at an output port of the edge-triggered flip-flop. The multiplexer circuit selectively outputs one of the plurality of input clock signals to a clock signal port of the edge-triggered flip-flop, based on a logic level of the output clock signal at the output port of the edge-triggered flip-flop, which is input to a select control port of the multiplexer circuit.

US Patent:

20200401413, Dec 24, 2020

Filed:

Jun 20, 2019

Appl. No.:

16/447588

Inventors:

- Armonk NY, US
Sunil SHUKLA - Scarsdale NY, US
Jungwook CHOI - Chappaqua NY, US
Silvia MUELLER - Altdorf, DE
Bruce FLEISCHER - Bedford Hills NY, US
Vijayalakshmi SRINIVASAN - New York NY, US
Ankur AGRAWAL - Chappaqua NY, US
Jinwook OH - Fort Lee NJ, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

G06F 9/38
G06F 15/80
G06F 5/06

Abstract:

Various embodiments are provided for using a reduced precision based programmable and single instruction multiple data (SIMD) dataflow architecture in a computing environment. One or more instructions between a plurality of execution units (EUs) operating in parallel within each one of a plurality of execution elements (EEs).

US Patent:

20200233642, Jul 23, 2020

Filed:

Apr 6, 2020

Appl. No.:

16/840847

Inventors:

- Armonk NY, US
Ankur Agrawal - White Plains NY, US
Bruce Fleischer - Bedford Hills NY, US
Kailash Gopalakrishnan - San Jose CA, US
Dongsoo Lee - White Plains NY, US

International Classification:

G06F 7/499

Abstract:

Techniques for operating on and calculating binary floating-point numbers using an enhanced floating-point number format are presented. The enhanced format can comprise a single sign bit, six bits for the exponent, and nine bits for the fraction. Using six bits for the exponent can provide an enhanced exponent range that facilitates desirably fast convergence of computing-intensive algorithms and low error rates for computing-intensive applications. The enhanced format can employ a specified definition for the lowest binade that enables the lowest binade to be used for zero and normal numbers; and a specified definition for the highest binade that enables it to be structured to have one data point used for a merged Not-a-Number (NaN)/infinity symbol and remaining data points used for finite numbers. The signs of zero and merged NaN/infinity can be “don't care” terms. The enhanced format employs only one rounding mode, which is for rounding toward nearest up.