Ankit Srivastava

US Patent:

8111088, Feb 7, 2012

Filed:

Apr 26, 2010

Appl. No.:

12/767370

Inventors:

Ankit Srivastava - San Diego CA, US
Xiaohong Quan - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03K 19/0175
H03K 19/094

US Classification:

326 68, 326 82, 326 83

Abstract:

A level shifter and method are provided for balancing a duty cycle of a signal. An input circuit receives a differential logic signal with two complimentary logic levels. A level transition balancing circuit balances the rise and fall times of a level shifted version of each complimentary logic level during a transition from a first to a second of the logic levels and a level shift. A logic element stores and provides outputs of the level shifted versions of the logic levels. The level transition balancing circuit can include a capacitor in parallel with a transfer element for each input. The capacitor destabilizes inputs to the logic element and balances the transition using a capacitance and a level previously stored in the logic element.

US Patent:

8373267, Feb 12, 2013

Filed:

Aug 2, 2011

Appl. No.:

13/196404

Inventors:

Junjun Li - Williston VT, US
Ankit Srivastava - Champaign IL, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/66
H01L 23/62

US Classification:

257713, 257174, 257362, 257E29181

Abstract:

A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

US Patent:

8390355, Mar 5, 2013

Filed:

Feb 22, 2011

Appl. No.:

13/032326

Inventors:

Xiaohong Quan - San Diego CA, US
Ankit Srivastava - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03H 11/26

US Classification:

327261, 327262

Abstract:

An integrated circuit for delaying a clock signal using a delay cell is described. The integrated circuit includes a current starved inverter. The current starved inverter includes a switched capacitor current source with a first dummy inverter, a first amplifier coupled to the first dummy inverter and a first capacitor coupled to the first amplifier via a first switch. The current starved inverter also includes a first transistor coupled to the current source. The integrated circuit also includes a second capacitor. A delay applied to the clock signal is dependent on a ratio between the first capacitor and the second capacitor. The first capacitor and the second capacitor may be located in proximity such that process, voltage and temperature variations affect the first capacitor and the second capacitor similarly and the delay applied to the clock signal is independent of process, voltage and temperature variations.

US Patent:

8446204, May 21, 2013

Filed:

Jan 27, 2011

Appl. No.:

13/014740

Inventors:

Ankit Srivastava - San Diego CA, US
Xuhao Huang - San Diego CA, US
Xiaohong Quan - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H03L 5/00
H03K 3/00

US Classification:

327333, 327205

Abstract:

A high voltage tolerant single ended receiver circuit includes a voltage divider that is operative to divide in half single ended input signals that are greater than the threshold voltages of the voltage divider. A pass gate circuit is operative to receive single ended signals that are below the threshold voltages of the voltage divider. Output from the voltage divider is coupled to a first input of a modified Schmitt trigger circuit to control a high threshold level of the Schmitt trigger circuit. Output from the pass gate circuit is coupled to a second input of the modified Schmitt trigger circuit to control a low threshold level of the Schmitt trigger circuit.

US Patent:

8538362, Sep 17, 2013

Filed:

Jul 16, 2010

Appl. No.:

12/837902

Inventors:

Ankit Srivastava - San Diego CA, US
Xiaohong Quan - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04B 1/10

US Classification:

455218, 455222

Abstract:

A squelch detection circuit and method involves a first comparator coupled to a complimentary input signal pair and having a first polarity output. A second comparator coupled to the complimentary input signal pair has a second polarity output. An offset associated with complimentary input signal pair establishes a positive squelch threshold and a negative squelch threshold. A calibration unit coupled to the first comparator and the second comparator generates a digital output including threshold settings and calibration settings to the first comparator and to the second comparator. The digital output can be associated with establishing the offset and with calibrating the positive squelch threshold and the negative squelch threshold.

US Patent:

8576523, Nov 5, 2013

Filed:

Mar 14, 2011

Appl. No.:

13/047683

Inventors:

Ankit Srivastava - San Diego CA, US
Eugene R. Worley - Irvine CA, US
Guoqing Miao - San Diego CA, US
Xiaohong Quan - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H02H 9/00
H02H 1/00
H02H 1/04
H02H 3/22

US Classification:

361 56, 361118

Abstract:

Techniques for electrostatic discharge (ESD) protection for amplifiers and other circuitry employing charge pumps. In an exemplary embodiment, a Vneg switch coupling a second flying capacitor node to a negative output voltage node is closed in response to an ESD event being detected between a supply voltage node and the negative output voltage node. A ground switch coupling a ground node to the second flying capacitor node is closed in response to an ESD event being detected between the ground node and the negative output voltage node. The Vneg switch is further closed in response to the ESD event being detected between the ground node and the negative output voltage node. Further techniques are disclosed for providing on-chip snapback clamps at the output of a power amplifier coupled to the charge pump to protect against ESD events as defined by the standard IEC 61000-4-2.

US Patent:

8637900, Jan 28, 2014

Filed:

Nov 27, 2012

Appl. No.:

13/686422

Inventors:

Junjun Li - Williston VT, US
Ankit Srivastava - Champaign IL, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

H01L 29/66

US Classification:

257173, 257174

Abstract:

A structure includes first and second silicon controlled rectifiers (SCRs) formed in a substrate. The first and the second SCRs each include at least one component commonly shared between the first and the second SCRs.

US Patent:

20090310267, Dec 17, 2009

Filed:

Jun 17, 2008

Appl. No.:

12/140485

Inventors:

Junjun Li - Williston VT, US
Ankit Srivastava - Champaign IL, US

Assignee:

INTERNATIONAL BUSINESS MACHINES CORPORATION - Armonk NY

International Classification:

H02H 9/00

US Classification:

361 56

Abstract:

A hardware description language (HDL) design structure encoded on a machine readable data storage medium, the HDL design comprising elements that when processed in a computer aided design system generates a machine executable representation of a device for implementing dynamic refresh protocols for DRAM based cache. The HDL design structure further comprises an integrated circuit having a differential driver, comprising: a first driver and a second driver forming the differential driver, the drivers are coupled in parallel between a first voltage source and a second voltage source; a first switch coupled to the first driver and configured to turn off the first driver during an ESD event such that the first driver sustains stress during the ESD event; and a second switch coupled to the second driver and configured to turn off the second driver during the ESD event such that the second driver sustains stress during the ESD event.