Salvador Palanca - Folsom CA Shekoufeh Qawami - El Dorado Hills CA Niranjan L. Cooray - Folsom CA Angad Narang - Rancho Cordova CA Subramaniam Maiyuran - Fair Oaks CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712 23
Abstract:
The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
Shared Cache Structure For Temporal And Non-Temporal Instructions
Salvador Palanca - Folsom CA Niranjan L. Cooray - Folsom CA Angad Narang - Rancho Cordova CA Vladimir Pentkovski - Folsom CA Steve Tsai - Rancho Cordova CA
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
Method And Apparatus For Prefetching Data Into Cache
Salvador Palanca - Folsom CA Niranjan L. Cooray - Folsom CA Angad Narang - Rancho Cordova CA Vladimir Pentkovski - Folsom CA Steve Tsai - Rancho Cordova CA Subramaniam Maiyuran - Fair Oaks CA Jagannath Keshava - Folsom CA Hsien-Hsin Lee - El Dorado Hills CA Steve Spangler - El Dorado Hills CA Suresh Kuttuva - Folsom CA Praveen Mosur - Folsom CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711138, 711137
Abstract:
A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
Method And System For Optimizing Write Combining Performance In A Shared Buffer Structure
Salvador Palanca - Folsom CA Vladimir Pentkovski - Folsom CA Niranjan L. Cooray - Folsom CA Subramaniam Maiyuran - Fair Oaks CA Angad Narang - Rancho Cordova CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 506
US Classification:
711154
Abstract:
An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.
Salvador Palanca - Folsom CA Shekoufeh Qawami - El Dorado Hills CA Niranjan L. Cooray - Folsom CA Angad Narang - Rancho Cordova CA Subramaniam Maiyuran - Fair Oaks CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 930
US Classification:
712 23
Abstract:
The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
Shared Cache Structure For Temporal And Non-Temporal Information Using Indicative Bits
Salvador Palanca - Solsom CA Niranjan L. Cooray - Folsom CA Angad Narang - Rancho Cordova CA Vladimir Pentkovski - Folsom CA Steve Tsai - Rancho Cordova CA
Assignee:
Intel Corporation - Santa Clara CA
International Classification:
G06F 1200
US Classification:
711133
Abstract:
A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
Cisco Systems since Apr 2012
Senior Product Manager, Catalyst 6500
Infineta Systems Oct 2011 - Apr 2012
Director, Business Development
Infineta Systems - San Jose, California Oct 2009 - Apr 2012
Director, FPGA Development
Cisco Dec 2007 - Oct 2009
Manager, Hardware Engineering
Cisco Mar 2006 - Dec 2007
Technical Leader
Education:
University of California, Berkeley - Walter A. Haas School of Business 2011
MBA, Entrepreneurship and Marketing
University of Florida 1992 - 1994
MS, Electrical Engineering
Institute of Technology, BHU 1988 - 1992
B. Tech, Electronics and Communication Engineering
Skills:
Fpga Asic Go To Market Strategy Hardware Architecture Ethernet Cisco Technologies Product Management Hardware Competitive Analysis Semiconductors Embedded Systems Product Lifecycle Management Strategy Testing Algorithms System Architecture Business Strategy Product Development Storage Product Launch Data Protection Marketing Strategy Cisco Networking Business Analysis Product Definition Deduplication Srdf Intel Cpu Design Processors Networking Hyper V Virtualization Commvault Replication Technologies Pricing Strategy