Angad Narang

US Patent:

6526499, Feb 25, 2003

Filed:

Jan 10, 2001

Appl. No.:

09/758486

Inventors:

Salvador Palanca - Folsom CA
Shekoufeh Qawami - El Dorado Hills CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Subramaniam Maiyuran - Fair Oaks CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712 23

Abstract:

The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.

US Patent:

6584547, Jun 24, 2003

Filed:

Mar 9, 2001

Appl. No.:

09/803357

Inventors:

Salvador Palanca - Folsom CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Vladimir Pentkovski - Folsom CA
Steve Tsai - Rancho Cordova CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711133, 711136, 711128, 711145, 711144, 711154, 711155, 711156

Abstract:

A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

US Patent:

6643745, Nov 4, 2003

Filed:

Mar 31, 1998

Appl. No.:

09/053383

Inventors:

Salvador Palanca - Folsom CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Vladimir Pentkovski - Folsom CA
Steve Tsai - Rancho Cordova CA
Subramaniam Maiyuran - Fair Oaks CA
Jagannath Keshava - Folsom CA
Hsien-Hsin Lee - El Dorado Hills CA
Steve Spangler - El Dorado Hills CA
Suresh Kuttuva - Folsom CA
Praveen Mosur - Folsom CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711138, 711137

Abstract:

A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.

US Patent:

61227153, Sep 19, 2000

Filed:

Mar 31, 1998

Appl. No.:

9/053384

Inventors:

Salvador Palanca - Folsom CA
Vladimir Pentkovski - Folsom CA
Niranjan L. Cooray - Folsom CA
Subramaniam Maiyuran - Fair Oaks CA
Angad Narang - Rancho Cordova CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 506

US Classification:

711154

Abstract:

An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.

US Patent:

62162152, Apr 10, 2001

Filed:

Apr 2, 1998

Appl. No.:

9/053932

Inventors:

Salvador Palanca - Folsom CA
Shekoufeh Qawami - El Dorado Hills CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Subramaniam Maiyuran - Fair Oaks CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712 23

Abstract:

The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.

US Patent:

6202129, Mar 13, 2001

Filed:

Mar 31, 1998

Appl. No.:

9/053386

Inventors:

Salvador Palanca - Solsom CA
Niranjan L. Cooray - Folsom CA
Angad Narang - Rancho Cordova CA
Vladimir Pentkovski - Folsom CA
Steve Tsai - Rancho Cordova CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711133

Abstract:

A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.