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Angad Narang

age ~54

from Los Altos, CA

Also known as:
  • Narang Angad
Phone and address:
1503 Topar Ave, Los Altos, CA 94024
650 559-1989

Angad Narang Phones & Addresses

  • 1503 Topar Ave, Los Altos, CA 94024 • 650 559-1989
  • 998 Starflower Ct, Sunnyvale, CA 94086 • 408 736-3735 • 408 746-3719
  • 135 Acalanes Dr, Sunnyvale, CA 94086 • 650 938-3898
  • 155 Acalanes Dr, Sunnyvale, CA 94086 • 650 938-3898
  • Santa Monica, CA
  • 2330 Vehicle Dr, Rancho Cordova, CA 95670 • 916 631-9255
  • Gainesville, FL
  • Folsom, CA
  • Foster City, CA
  • Santa Clara, CA
  • Los Angeles, CA
  • 998 Starflower Ct, Sunnyvale, CA 94086 • 408 631-4255

Work

  • Company:
    Cisco systems
    Apr 2012
  • Position:
    Senior product manager, catalyst 6500

Education

  • Degree:
    MBA
  • School / High School:
    University of California, Berkeley - Walter A. Haas School of Business
    2011
  • Specialities:
    Entrepreneurship and Marketing

Skills

Fpga • Asic • Go To Market Strategy • Hardware Architecture • Ethernet • Cisco Technologies • Product Management • Hardware • Competitive Analysis • Semiconductors • Embedded Systems • Product Lifecycle Management • Strategy • Testing • Algorithms • System Architecture • Business Strategy • Product Development • Storage • Product Launch • Data Protection • Marketing Strategy • Cisco Networking • Business Analysis • Product Definition • Deduplication • Srdf • Intel • Cpu Design • Processors • Networking • Hyper V • Virtualization • Commvault • Replication Technologies • Pricing Strategy

Industries

Computer Networking

Us Patents

  • Method And Apparatus For Load Buffers

    view source
  • US Patent:
    6526499, Feb 25, 2003
  • Filed:
    Jan 10, 2001
  • Appl. No.:
    09/758486
  • Inventors:
    Salvador Palanca - Folsom CA
    Shekoufeh Qawami - El Dorado Hills CA
    Niranjan L. Cooray - Folsom CA
    Angad Narang - Rancho Cordova CA
    Subramaniam Maiyuran - Fair Oaks CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 930
  • US Classification:
    712 23
  • Abstract:
    The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
  • Shared Cache Structure For Temporal And Non-Temporal Instructions

    view source
  • US Patent:
    6584547, Jun 24, 2003
  • Filed:
    Mar 9, 2001
  • Appl. No.:
    09/803357
  • Inventors:
    Salvador Palanca - Folsom CA
    Niranjan L. Cooray - Folsom CA
    Angad Narang - Rancho Cordova CA
    Vladimir Pentkovski - Folsom CA
    Steve Tsai - Rancho Cordova CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 1200
  • US Classification:
    711133, 711136, 711128, 711145, 711144, 711154, 711155, 711156
  • Abstract:
    A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.
  • Method And Apparatus For Prefetching Data Into Cache

    view source
  • US Patent:
    6643745, Nov 4, 2003
  • Filed:
    Mar 31, 1998
  • Appl. No.:
    09/053383
  • Inventors:
    Salvador Palanca - Folsom CA
    Niranjan L. Cooray - Folsom CA
    Angad Narang - Rancho Cordova CA
    Vladimir Pentkovski - Folsom CA
    Steve Tsai - Rancho Cordova CA
    Subramaniam Maiyuran - Fair Oaks CA
    Jagannath Keshava - Folsom CA
    Hsien-Hsin Lee - El Dorado Hills CA
    Steve Spangler - El Dorado Hills CA
    Suresh Kuttuva - Folsom CA
    Praveen Mosur - Folsom CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 1200
  • US Classification:
    711138, 711137
  • Abstract:
    A computer system is disclosed. The computer system includes a higher level cache, a lower level cache, a decoder to decode instructions, and a circuit coupled to the decoder. In one embodiment, the circuit, in response to a single decoded instruction, retrieves data from external memory and bypasses the lower level cache upon a higher level cache miss. In another embodiment, the circuit, in response to a first decoded instruction, issues a request to retrieve data at an address from external memory to place said data only in the lower level cache, detects a second cacheable decoded instruction to said address, and places said data in the higher level cache.
  • Method And System For Optimizing Write Combining Performance In A Shared Buffer Structure

    view source
  • US Patent:
    61227153, Sep 19, 2000
  • Filed:
    Mar 31, 1998
  • Appl. No.:
    9/053384
  • Inventors:
    Salvador Palanca - Folsom CA
    Vladimir Pentkovski - Folsom CA
    Niranjan L. Cooray - Folsom CA
    Subramaniam Maiyuran - Fair Oaks CA
    Angad Narang - Rancho Cordova CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 506
  • US Classification:
    711154
  • Abstract:
    An apparatus and method of optimizing write combining operations using write combining buffers. A plurality of control fields are assigned to each of the write combining buffers. Each of the control fields has a value corresponding to one of a plurality of write combining states. A first of the plurality of write combining states transitions to a second of the plurality of write combining states in response to a write combining operation.
  • Method And Apparatus For Senior Loads

    view source
  • US Patent:
    62162152, Apr 10, 2001
  • Filed:
    Apr 2, 1998
  • Appl. No.:
    9/053932
  • Inventors:
    Salvador Palanca - Folsom CA
    Shekoufeh Qawami - El Dorado Hills CA
    Niranjan L. Cooray - Folsom CA
    Angad Narang - Rancho Cordova CA
    Subramaniam Maiyuran - Fair Oaks CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 930
  • US Classification:
    712 23
  • Abstract:
    The present invention discloses a method and apparatus for implementing a senior load instruction type. An instruction requesting a memory reference is decoded. The decoded instruction is then dispatched to a memory ordering unit. The instruction is retired from a load buffer and is executed after retiring.
  • Shared Cache Structure For Temporal And Non-Temporal Information Using Indicative Bits

    view source
  • US Patent:
    6202129, Mar 13, 2001
  • Filed:
    Mar 31, 1998
  • Appl. No.:
    9/053386
  • Inventors:
    Salvador Palanca - Solsom CA
    Niranjan L. Cooray - Folsom CA
    Angad Narang - Rancho Cordova CA
    Vladimir Pentkovski - Folsom CA
    Steve Tsai - Rancho Cordova CA
  • Assignee:
    Intel Corporation - Santa Clara CA
  • International Classification:
    G06F 1200
  • US Classification:
    711133
  • Abstract:
    A method and system for providing cache memory management. The system comprises a main memory, a processor coupled to the main memory, and at least one cache memory coupled to the processor for caching of data. The at least one cache memory has at least two cache ways, each comprising a plurality of sets. Each of the plurality of sets has a bit which indicates whether one of the at least two cache ways contains non-temporal data. The processor accesses data from one of the main memory or the at least one cache memory.

Resumes

Angad Narang Photo 1

Senior Director, Product Management

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Location:
San Francisco, CA
Industry:
Computer Networking
Work:
Cisco Systems since Apr 2012
Senior Product Manager, Catalyst 6500

Infineta Systems Oct 2011 - Apr 2012
Director, Business Development

Infineta Systems - San Jose, California Oct 2009 - Apr 2012
Director, FPGA Development

Cisco Dec 2007 - Oct 2009
Manager, Hardware Engineering

Cisco Mar 2006 - Dec 2007
Technical Leader
Education:
University of California, Berkeley - Walter A. Haas School of Business 2011
MBA, Entrepreneurship and Marketing
University of Florida 1992 - 1994
MS, Electrical Engineering
Institute of Technology, BHU 1988 - 1992
B. Tech, Electronics and Communication Engineering
Skills:
Fpga
Asic
Go To Market Strategy
Hardware Architecture
Ethernet
Cisco Technologies
Product Management
Hardware
Competitive Analysis
Semiconductors
Embedded Systems
Product Lifecycle Management
Strategy
Testing
Algorithms
System Architecture
Business Strategy
Product Development
Storage
Product Launch
Data Protection
Marketing Strategy
Cisco Networking
Business Analysis
Product Definition
Deduplication
Srdf
Intel
Cpu Design
Processors
Networking
Hyper V
Virtualization
Commvault
Replication Technologies
Pricing Strategy

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Youtube

ANGAD Narang

Amandeep beutiful son with his uncle.

  • Duration:
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Ankit narang [Angad Sakhuja] Lifestyle_Girlfr...

Ankit narang [Angad Sakhuja] Lifestyle_Girlfr... Worth_Tellywood_... ...

  • Duration:
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Love Marriage Ke Adjustments I Angad Singh Ra...

Edit: Jayant Kaushik Title Animation : Sandip Gediya Sound : Srejit Me...

  • Duration:
    9m 39s

EIC: Choose Your Friends - Angad Singh Ranyal...

It's too late for Angad but he tries to convince 25 year olds to choos...

  • Duration:
    3m 52s

Pure Storage Named by IT Pros 2017 Innovation...

Angad Narang, Director, Product Management, talks about the technology...

  • Duration:
    1m 3s

Ishleen & Angad Engagement Montage

Vaaho Photo 516-681-3040.

  • Duration:
    3m 15s

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