Andrew B White

US Patent:

20220414625, Dec 29, 2022

Filed:

Jun 29, 2021

Appl. No.:

17/362698

Inventors:

- Austin TX, US
Andrew J. White - Austin TX, US

Assignee:

Closinglock, LLC - Austin TX

International Classification:

G06Q 20/10
G06Q 20/38
G06Q 50/16

Abstract:

A method may comprise: receiving, via a secure payment system, transaction information associated with a real estate transaction, the transaction information including an escrow account, a buyer name, and a buyer contact, the escrow account configured to receive a good funds payment for an earnest money deposit or a closing payment; receiving, via the secure payment system, a first request to transfer the good funds payment from a user account of a user to the escrow account; querying, via the secure payment system, information associated with the user account; generating, via the secure payment system, a second request for payment to a financial institution of the user account; receiving, via the secure payment system, a notification that the second request for payment was approved by the user; and in response to receiving the notification, transferring the good funds payment from the user account of the user to a secure payment account of the secure payment system.

US Patent:

20170357705, Dec 14, 2017

Filed:

Jun 8, 2016

Appl. No.:

15/177068

Inventors:

- San Diego CA, US
Andrew White - Austin TX, US

International Classification:

G06F 17/30
G06F 1/32

Abstract:

In an illustrative example, a method of operation of an electronic device includes identifying a plurality of threads. Each thread of the plurality of threads is configured to execute a plurality of instructions including a barrier instruction corresponding to a target of a synchronization operation. The method further includes selecting a master thread to perform one or more operations associated with the synchronization operation. The method also includes providing an indication of a number of threads included in the plurality of threads to the master thread.

US Patent:

20170262318, Sep 14, 2017

Filed:

Mar 11, 2016

Appl. No.:

15/068166

Inventors:

- San Diego CA, US
Andrew White - Austin TX, US
Jerome V. Coffin - San Diego CA, US
Michael George Creamer - San Diego CA, US

International Classification:

G06F 9/52

Abstract:

In one aspect, a method implemented by a first sync controller includes receiving sync information, wherein the sync information (i) identifies a first sync process, (ii) indicates that the first sync controller is not a master controller of the first sync process, and (iii) identifies a group of components executing the first sync process, the group comprising a first processing device; receiving a first sync indication from the first processing device; storing an indication, associated with the first sync process, that the first sync indication was received from the first processing device; determining that a sync indication has been received from all components of the first group of components; and transmitting a second sync indication to a second sync controller.

US Patent:

20170220520, Aug 3, 2017

Filed:

Jan 29, 2016

Appl. No.:

15/010091

Inventors:

- San Diego CA, US
Andrew J. White - Austin TX, US

Assignee:

KnuEdge Incorporated - San Diego CA

International Classification:

G06F 15/80

Abstract:

Systems and methods for operating a processing device are provided. A method may comprise transmitting data on the processing device, monitoring state information for a plurality of buffers on the processing device for the transmitted data, aggregating the monitored state information, starting a timer in response to determining that all buffers of the plurality of buffers are empty and asserting a drain state for the plurality of buffers in response to all buffers of the plurality of buffers remained empty for the duration of the timer.

US Patent:

20170153993, Jun 1, 2017

Filed:

Nov 30, 2015

Appl. No.:

14/953594

Inventors:

- San Diego CA, US
Jerome Vincent Coffin - San Diego CA, US
Andrew Jonathan White - Austin TX, US
Ramon Zuniga - San Diego CA, US

Assignee:

KNUEDGE, INC. - San Diego CA

International Classification:

G06F 13/28
G06F 15/78
G06F 13/16

Abstract:

A multiprocessor architecture utilizing direct memory access (DMA) processors that execute programmed code to feed data to one or more processor cores in advance of those cores requesting data. Stalls of the processor cores are minimized by continually feeding new data directly into the data registers within the cores. When different data is needed, the processor cores can redirect a DMA processor to execute a different feeder program, or to jump to a different point in the feeder program it is already executing. The DMA processors can also feed executable instructions into the instruction pipelines of the processor cores, allowing the feeder program to orchestrate overall processor operations.

US Patent:

20170116154, Apr 27, 2017

Filed:

Oct 23, 2015

Appl. No.:

14/921377

Inventors:

- San Diego CA, US
Andrew White - Austin TX, US

Assignee:

THE INTELLISIS CORPORATION - San Diego CA

International Classification:

G06F 15/82
G06F 9/30

Abstract:

A network on a chip processor uses uniform addressing for both conventional memory and operand registers. The processor contains a large number of processing elements (e.g., 256). Each processing element has a number (e.g., 200) of operand registers to which it has direct, high-speed (e.g., single clock-cycle) access. Each of these operand registers is also assigned a global memory address, so other processing elements can read or write those operand registers as if they were located in main memory. Software that expects communication between processing elements to happen via memory can use memory-based reads/writes, but gain substantial speed by writing that data directly to the operand registers used for execution of instructions by the target processor.

US Patent:

20140324491, Oct 30, 2014

Filed:

Apr 29, 2013

Appl. No.:

13/872470

Inventors:

- Armonk NY, US
James E. Varan - Austin TX, US
Jeffrey L. Wilson - Bastrop TX, US
Andrew P. White - Sheridan WY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06Q 10/08

US Classification:

705 712

Abstract:

Assigning parts to storage locations in a warehouse. Ratings of parts are determined based partially on pick frequencies of the parts. The parts with higher pick frequencies are determined to have higher ratings than parts with lower pick frequencies. Grades of storage locations in the warehouse are determined based partially on accessibilities of the storage locations to a loading dock. A programmed processor determines respective ranges of grades of the storage locations that will satisfy storage location criteria of the respective ratings of the parts such that the higher rated parts have narrower respective ranges of grades of satisfactory storage locations than the lower rated parts.

Author:

Andrew J. White

ISBN #:

0950036048

Author:

Andrew J. White

ISBN #:

0950036099

Author:

Andrew White

ISBN #:

0140278974

Author:

Andrew White

ISBN #:

0140287213

Author:

Andrew White

ISBN #:

0140296220

Author:

Andrew White

ISBN #:

0141003537

Author:

Andrew White

ISBN #:

0072224711

Author:

Andrew White

ISBN #:

0130407607