Andrew R Wheeler

US Patent:

7500056, Mar 3, 2009

Filed:

Jul 21, 2004

Appl. No.:

11/089586

Inventors:

Andrew Ray Wheeler - Fort Collins CO, US
James Robert Peterson - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711118, 711137

Abstract:

One disclosed embodiment may comprise a computer system that includes at least one processor having at least one cache. An interface includes an associated cache, the interface preloading the associated cache with instruction data acquired from non-volatile memory as part of a reset sequence so that the instruction data in the associated cache is available to the at least one cache of the at least one processor to facilitate reset by the computer system.

US Patent:

7519802, Apr 14, 2009

Filed:

May 5, 2004

Appl. No.:

10/838981

Inventors:

Andrew Ray Wheeler - Fort Collins CO, US
James Robert Peterson - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/00
G06F 9/24
G06F 15/177

US Classification:

713 1, 713 2, 713100

Abstract:

Systems and methods for configuring a computer system are disclosed. One embodiment of a system may comprise memory that stores configuration data for a plurality of components of a computer system. A configuration system operates to access the configuration data from the memory and to program at least one of the plurality of components based on corresponding configuration data from the memory while inhibiting operation of at least another portion of the computer system.

US Patent:

7856549, Dec 21, 2010

Filed:

Jan 24, 2007

Appl. No.:

11/657144

Inventors:

Andrew R. Wheeler - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 15/16

US Classification:

713 1, 713 2, 718 1, 709223

Abstract:

A system for dynamically regulating power consumption in an information technology (IT) infrastructure having a plurality of compute nodes interconnected over a network is provided. The system includes at least one virtual machine (VM) host deployed at each of the plurality of compute nodes, the at least one VM host is operable to host at least one VM guest, and the VM hosts on different ones of the plurality of compute nodes are version compatible to enable migration of the VM guests among the VM hosts. The system further includes a management module connected to the plurality of compute nodes over the network to receive a native measurement of a performance metric of a computing resource in each of the plurality of compute nodes, the management module is operable to dynamically regulate power consumption of the plurality of compute nodes by migrating the VM guests among the VM hosts based at least on the received performance metrics of the plurality of compute nodes.

US Patent:

8234459, Jul 31, 2012

Filed:

Mar 13, 2009

Appl. No.:

12/403712

Inventors:

Blaine D. Gaither - Fort Collins CO, US
Andrew R. Wheeler - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 12/00

US Classification:

711147, 711103, 711114, 711170, 711202

Abstract:

A switch module having shared memory that is allocated to other blade servers. A memory controller partitions and enables access to partitions of the shared memory by requesting blade servers.

US Patent:

8307259, Nov 6, 2012

Filed:

Jan 5, 2009

Appl. No.:

12/319266

Inventors:

Andrew Ray Wheeler - Fort Collins CO, US
James R. Peterson - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G11C 29/00

US Classification:

714764

Abstract:

This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

US Patent:

8612973, Dec 17, 2013

Filed:

Sep 26, 2007

Appl. No.:

11/861846

Inventors:

Chris M. Giles - Lafayette CO, US
Russ W. Herrell - Fort Collins CO, US
John A. Morrison - Fort Collins CO, US
John R. Planow - Sacramento CA, US
Joseph F. Orth - Fort Collins CO, US
Andrew R. Wheeler - Fort Collins CO, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 9/455

US Classification:

718 1, 710260, 710268, 711165

Abstract:

A method and system for handling interrupts within a computer system during hardware resource migration are disclosed. In at least some embodiments, the method includes (a) programming an address conversion component so that incoming interrupt signals are directed to a control component rather than to a source processing resource, and (b) accumulating the incoming interrupt signals at the control component. Additionally the method also includes, subsequent to the migration of the partition from the source processing resource to a destination processing resource, (c) sending the accumulated incoming interrupt signals to the destination processing resource, and (d) reprogramming the address conversion component so that further incoming interrupt signals are directed to the destination processing resource.

US Patent:

20060212778, Sep 21, 2006

Filed:

Mar 16, 2005

Appl. No.:

11/081335

Inventors:

Andrew Wheeler - Fort Collins CO, US
James Peterson - Fort Collins CO, US

International Classification:

H03M 13/00
G11C 29/00

US Classification:

714764000

Abstract:

This application relates to hardware based memory scrubbing. One disclosed embodiment may comprise a system that includes an engine, implemented in hardware, configured to initiate a request for data residing in associated memory. An error system is configured to detect errors in data that has been read from associated memory in response to the request for the data, the error system maintaining a log of entries corresponding to errors detected by the error system. An identifier is associated with each of the entries in the log that result from the request initiated by the engine to differentiate from other entries in the log.

US Patent:

20100273177, Oct 28, 2010

Filed:

Dec 10, 2007

Appl. No.:

12/517774

Inventors:

Roger N. Piasio - Cumberland Foreside ME, US
Nathan Turner - Portland ME, US
Andrew Wheeler - Saco ME, US

International Classification:

G01N 33/53

US Classification:

435 71

Abstract:

Provided are methods and devices for performing sensitive, rapid antigen testing of saliva, which yield sensitivity comparable to both rapid antigen tests and saliva culture.

Address:

8288 Sand Dollar Dr, Windsor, CO 80528

VIN:

2HNYD28267H535410

Make:

ACURA

Model:

MDX

Year:

2007