Andrew F Glew

US Patent:

6378062, Apr 23, 2002

Filed:

Mar 28, 1997

Appl. No.:

08/825427

Inventors:

Jeffery M. Abramson - Aloha OR
Haitham Akkary - Portland OR
Andrew F. Glew - Hillsboro OR
Glenn J. Hinton - Portland OR
Kris G. Konigsfeld - Portland OR
Paul D. Madland - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 930

US Classification:

712208, 712200, 712211, 712216

Abstract:

The present invention provides for executing store instructions with a processor. The present invention executes each of the store instructions by producing the data that is to be stored and by calculating the destination address to which the data is to be stored. In the present invention, the store instructions are executed to produce the destination address of the store instruction earlier than the prior art.

US Patent:

6647482, Nov 11, 2003

Filed:

Apr 7, 2000

Appl. No.:

09/545056

Inventors:

Ronny Ronen - Haifa, IL
Andrew F. Glew - Portland OR
Maury J. Bach - Haifa, IL
Robert C. Valentine - Kiryat Tivon, IL
Richard A. Uhlig - Hillsboro OR
Opher D. Kahn - Zichron Yacov, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204

US Classification:

711212, 711201, 711208, 711219

Abstract:

Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

US Patent:

6678816, Jan 13, 2004

Filed:

May 19, 2003

Appl. No.:

10/441397

Inventors:

Ronny Ronen - Haifa, IL
Andrew F. Glew - Portland OR
Maury J. Bach - Haifa, IL
Robert Valentine - Kiryat Tivon, IL
Richard A. Uhlig - Hillsboro OR
Opher D. Kahn - Zichron Yacov, IL

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1204

US Classification:

711212, 711201, 711208, 711219

Abstract:

Method for producing a predetermined length page memory pointer record, according to a selected page size and a selected page address, the method including the procedures of: determining a dynamic location of a separator bit within the page memory pointer record, according to the selected page size and an initial page size, the initial page size being respective of the smallest page size in a given memory system, writing a predetermined value to the dynamic location, writing a sequence of values opposite to the predetermined value to selected page size bits of the page memory pointer record, when the selected page size is different than the initial page size, and writing the selected page address to selected page address bits of the page memory pointer record.

US Patent:

6792523, Sep 14, 2004

Filed:

Jul 27, 1999

Appl. No.:

09/363116

Inventors:

Andrew F. Glew - Hillsboro OR
Larry M. Menneneier - Boulder Creek CA
Alexander D. Peleg - Haifa, IL
David Bistry - Cupertino CA
Millind Mittal - South San Francisco CA
Carole Dulong - Saratoga CA
Eiichi Kowashi - Ibaraki, JP
Benny Eitan - Haifa, IL
Derrik Lin - Foster City CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

712228, 712222, 712217, 712229, 712244, 712 23, 711221, 709108

Abstract:

A processor with instructions to operate on different data types stored in a single logical register file. According to one aspect of the invention, a first set of instructions of a first instruction type operates on the contents of what at least logically appears to software as a single logical register file. The first set of instructions appears to access the single logical register file as a flat register file. In addition, a first instruction of a second instruction type operates on the logical register file. However, the first instruction appears to access the logical register file as a stack referenced register file. Furthermore, sometime between starting the execution of the first set of instructions and completing the execution of the first instruction, all tags in a set of tags indicating whether corresponding registers in the single logical register file are empty or non-empty are caused to indicate non-empty states.

US Patent:

7149882, Dec 12, 2006

Filed:

May 11, 2004

Appl. No.:

10/844606

Inventors:

Andrew F. Glew - Hillsboro OR, US
Larry M. Mennemeier - Boulder Creek CA, US
Alexander D. Peleg - Haifa, IL
David Bistry - Cupertino CA, US
Millind Mittal - South San Francisco CA, US
Carole Dulong - Saratoga CA, US
Eiichi Kowashi - Ibaraki, JP
Benny Eitan - Haifa, IL
Derrik Lin - Foster City CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/38

US Classification:

712222, 712221, 712228, 712229

Abstract:

A processor with instructions to operate on different data types stored in a single logical register file. According to one embodiment of the invention, a processor includes a number of physical registers, a memory unit, and a decode/execution unit. The memory unit is to make the number of physical registers appear to software as a single software-visible register file. The decode/execution unit is to execute on the contents of the single software-visible register file instructions of a first instruction type and of a second instruction type, wherein the single software-visible register file is to be operated as a flat register file during execution of instructions of the second instruction type and as a stack referenced register file during execution of instructions of the first instruction type.

US Patent:

7318141, Jan 8, 2008

Filed:

Dec 17, 2002

Appl. No.:

10/322003

Inventors:

Steve M. Bennett - Hillsboro OR, US
Gilbert Neiger - Portland OR, US
Erik C. Cota-Robles - Portland OR, US
Stalinselvaraj Jeyasingh - Portland OR, US
Alain Kagi - Portland OR, US
Michael A. Kozuch - Export PA, US
Richard A. Uhlig - Hillsboro OR, US
Larry Smith - Beaverton OR, US
Dion Rodgers - Hillsboro OR, US
Andrew Glew - San Jose CA, US
Erich Boleyn - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/06

US Classification:

711202, 711203, 718 1

Abstract:

Methods and systems are provided to control the execution of a virtual machine (VM). A VM Monitor (VMM) accesses VM Control Structures (VMCS) indirectly through access instructions passed to a processor. In one embodiment, the access instructions include VMCS component identifiers used by the processor to determine the appropriate storage location for the VMCS components. The processor identifies the appropriate storage location for the VMCS component within the processor storage or within memory.

US Patent:

7644258, Jan 5, 2010

Filed:

Aug 29, 2005

Appl. No.:

11/215835

Inventors:

Andrew Forsyth Glew - Hillsboro OR, US

Assignee:

Searete, LLC - Bellevue WA

International Classification:

G06F 7/38
G06F 9/00
G06F 9/44
G06F 15/00

US Classification:

712239

Abstract:

Various embodiments are described relating to processors, branch predictors, branch prediction systems, and computing systems. In an example embodiment, a processor includes a plurality of branch predictors. Each branch predictor is adapted to provide a prediction and an override signal. In the example embodiment, the processor futher includs a branch prediction control circuit. The branch prediction circuit is adapted to generate a branch prediction based on the prediction and the override signal from each predictor.

US Patent:

8028152, Sep 27, 2011

Filed:

Oct 31, 2007

Appl. No.:

11/932874

Inventors:

Andrew Forsyth Glew - Hillsboro OR, US

Assignee:

The Invention Science Fund I, LLC - Bellevue WA

International Classification:

G06F 9/00

US Classification:

712220, 718 1, 712 32

Abstract:

A hierarchical microprocessor. An embodiment of a hierarchical microprocessor includes a plurality of first-level instruction pipeline elements; a plurality of execution clusters, where each execution cluster is operatively coupled with each of the first-level instruction pipeline elements. Each execution cluster includes a plurality of second-level instruction pipeline elements, where each of the second-level instruction pipeline elements corresponds with a respective first-level instruction pipeline element, and one or more instruction execution units operatively coupled with each of the second-level instruction pipeline elements, where the microprocessor is configured to execute multiple execution threads using the plurality of first-level instruction pipeline elements and the plurality of execution clusters.