Andrei E Vityaev

US Patent:

6456208, Sep 24, 2002

Filed:

Jun 30, 2000

Appl. No.:

09/607904

Inventors:

Nersi Nazari - Cupertino CA
Andrei Vityaev - Santa Clara CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

H03M 700

US Classification:

341 59, 341 81

Abstract:

In this invention a thirty three bit word is encoded from a thirty two bit word to conform to RLL coding constraints. A parity bit is added to the coded word after coding is complete. With the parity bit inserted the code satisfies a minimum Hamming weight of nine and no more than eleven consecutive zeros and no more than eleven consecutive zeros in both the odd and even interleaves. A table of âbadâ eight bit sequences is used to compare the odd and even interleaves of the right and left halves of the input word that is being encoded. If a âbadâ sequence is found, its position in the table points to a second table containing a four bit replacement code that is inserted into the coded output word. Flag bits in the output coded word are set to indicate the violation of the coding constraints and provide a means by which a decoder can be used to reverse the process and obtain the original input word.

US Patent:

6473010, Oct 29, 2002

Filed:

Jun 26, 2000

Appl. No.:

09/603188

Inventors:

Andrei Vityaev - Santa Clara CA
Zining Wu - Los Altos CA
Greg Burd - San Jose CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

H03M 700

US Classification:

341107

Abstract:

A design-based tool for determining an error correction code (ECC) failure probability of an iterative decoding algorithm provides a technique for testing the effectiveness of the algorithm before the integrated circuit implementing the algorithm is built.

US Patent:

6526530, Feb 25, 2003

Filed:

Dec 22, 1999

Appl. No.:

09/470170

Inventors:

Nersi Nazari - Cupertino CA
Andrei Vityaev - Santa Clara CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

G06F 1100

US Classification:

714701, 714758

Abstract:

Method and apparatus for encoding data using check bits for additional data protection, in addition to the time-varying maximum transition run code which eliminates data patterns producing long runs of consecutive transitions. The check bits are inserted into codewords in preselected locations. The time-varying maximum transition run code does not permit more than j transitions beginning from an even-numbered sample period and does not permit more than j+l transitions beginning from an odd-numbered sample period, wherein j 1. This time-varying maximum transition run constraint is preserved even after the check bits are inserted, regardless of the bit values of the check bits.

US Patent:

6711225, Mar 23, 2004

Filed:

May 26, 2000

Appl. No.:

09/578886

Inventors:

Pantas Sutardja - San Jose CA
Andrei Vityaev - Santa Clara CA

Assignee:

Marvell International, Ltd. - Hamilton

International Classification:

H04L 706

US Classification:

375364, 375366, 370509, 370514

Abstract:

A method and apparatus for data retrieval from a storage media, such as magnetic disk drive. A synchronization detector decodes the synchronization information from either the first or second synchronization mark. A later stage detector then carries out several decoding iterations using the synchronization information from the synchronization detector and data stored in the first and second memories. Loss of the data between the first synchronization mark and the second synchronization mark, if there is a problem with the first synchronization mark, is avoided because the bit stream is stored in the first memory.

US Patent:

6774825, Aug 10, 2004

Filed:

Sep 25, 2002

Appl. No.:

10/253909

Inventors:

William G. Bliss - Thornton CO
Andrei Vityaev - Santa Clara CA
Razmik Karabed - San Jose CA
Ali Najafi - Sunnyvale CA
Jonathan Ashley - Santa Clara CA

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03M 700

US Classification:

341 81, 714755

Abstract:

A system and method to modulate coding based on an ECC interleave structure include a first encoder encoding an input stream of bits comprising input blocks sorted into interleaves. A second encoder encodes a subset of the input blocks to produce output blocks, where the first encoder permutates a remainder of the input blocks and the output blocks to produce a codeword.

US Patent:

6788223, Sep 7, 2004

Filed:

Sep 25, 2002

Appl. No.:

10/253911

Inventors:

William G. Bliss - Thornton CO
Andrei Vityaev - Soquel CA
Razmik Karabed - San Jose CA

Assignee:

Infineon Technolgies NA Corp. - Alexandria VA

International Classification:

H03M 700

US Classification:

341 50, 341 51, 341 58

Abstract:

An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b , b , b. . . b to a coded sequence c , c , c. . . c. The selection circuit selects c in the coded sequence c , c , c. . . c such that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b , b , b. . . b to a sequence c , c. . . c , and a transition minimization circuit to add c to the sequence c , c. . . c. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c , c , c. . . c.

US Patent:

7053801, May 30, 2006

Filed:

Jun 18, 2004

Appl. No.:

10/869843

Inventors:

William G. Bliss - Thornton CO, US
Andrei Vityaev - Soquel CA, US
Razmik Karabed - San Jose CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03M 7/00

US Classification:

341 50, 341 51, 341 58

Abstract:

An apparatus has a conversion circuit, a precoder circuit, and a selection circuit. The conversion circuit converts user data b, b, b. . . bto a coded sequence c, c, c. . . c. The selection circuit selects cin the coded sequence c, c, c. . . csuch that the output of the precoder circuit has less than a maximum number q of transitions. The conversion circuit may include an encoder circuit to convert user data b, b, b. . . bto a sequence c, c. . . c, and a transition minimization circuit to add cto the sequence c, c. . . c. The apparatus may have a circuit to add at least one additional bit, which may be a parity bit, to the coded sequence c, c, c. . . c.

US Patent:

7178084, Feb 13, 2007

Filed:

Sep 25, 2002

Appl. No.:

10/253916

Inventors:

William G. Bliss - Thornton CO, US
Andrei Vityaev - Soquel CA, US
Razmik Karabed - San Jose CA, US

Assignee:

Infineon Technologies AG - Munich

International Classification:

H03M 13/00

US Classification:

714758, 714781

Abstract:

A data coding method produces codewords with a scheme that changes for different codewords, and decodes codewords with a scheme that remains constant for all codewords. The coding method receives k user bits, codes the user bits to produce k+r output bits, corrupts any one of the output bits, and accurately reproduces at least k−r−1 user bits. Codewords coded using the appropriate initial conditions are output. For each codeword, the appropriate initial conditions are appended to the codeword coded therefrom.