Andre Sturm

US Patent:

7492648, Feb 17, 2009

Filed:

Mar 24, 2006

Appl. No.:

11/387879

Inventors:

Andre Sturm - Essex Junction VT, US
Christopher Miller - Underhill VT, US
Wolfgang Hokenmaier - Burlington VT, US
Michael Killian - Richmond VT, US
Jochen Hoffman - Colchester VT, US

Assignee:

Infineon Technologies AG - Neubiberg

International Classification:

G11C 7/08
G11C 8/12

US Classification:

365195, 365196, 365200, 3652257, 36523003

Abstract:

A method for reducing defect leakage current in a semiconductor memory device comprising a plurality of memory banks, each memory bank comprising a plurality of memory arrays and sense amplifier columns comprising a plurality of sense amplifiers, wherein there is a sense amplifier column positioned between and shared by memory arrays on opposites thereof. At least one bank-specific isolation control signal is independently generated for each of the plurality of memory banks depending on existence and location of an anomalous bitline leakage in a memory bank. The at least one bank-specific isolation control signal is supplied to at least one sense amplifier column in the corresponding memory bank to isolate at least one side to at least one memory array that is in an unselected state in a corresponding memory bank.

US Patent:

7840876, Nov 23, 2010

Filed:

Feb 20, 2007

Appl. No.:

11/676774

Inventors:

Andre Sturm - Essex Junction VT, US
Harald Streif - Burlington VT, US

Assignee:

Qimonda AG - München

International Classification:

G11C 29/00

US Classification:

714766

Abstract:

The present invention includes a memory device with a data memory and an error correction code control circuit. The data memory stores data parity information for error correction. The error correction code control circuit is configured to receive a selection signal indicative of whether an error correction mode is to be used. Power to access the portion of the memory storing the parity information is disabled when the error correction mode is enabled.

US Patent:

20070223296, Sep 27, 2007

Filed:

Mar 24, 2006

Appl. No.:

11/387882

Inventors:

Christopher Miller - Underhill VT, US
Andre Sturm - Essex Junction VT, US
Wolfgang Hokenmaier - Burlington VT, US

International Classification:

G11C 7/02

US Classification:

365208000

Abstract:

A semiconductor memory device and method are provided in which leakage current of the memory device is reduced. A sense amplifier is isolated from a memory array that has an anomalous bitline leakage when the memory array is not selected.

US Patent:

20070247938, Oct 25, 2007

Filed:

Apr 25, 2006

Appl. No.:

11/410255

Inventors:

Christopher Miller - Underhill VT, US
Andre Sturm - Essex Junction VT, US

International Classification:

G11C 7/02

US Classification:

365207000

Abstract:

A method and memory device are provided in which sense nodes of a sense amplifier in a semiconductor memory device are internally precharged independent of equalize and precharge operations on bitlines of a memory array associated with the sense amplifier.

US Patent:

20080080232, Apr 3, 2008

Filed:

Sep 28, 2006

Appl. No.:

11/529569

Inventors:

Andre Sturm - Essex Junction VT, US
Hans-Heinrich Viehmann - Munich, DE
Dietmar Gogl - Essex Junction VT, US

International Classification:

G11C 11/00
G11C 11/14
G11C 11/15

US Classification:

365158, 365171, 365173

Abstract:

In a method of programming a magneto resistive memory cell, a first magnetic field is applied to the magneto resistive memory cell. It is determined whether the magneto resistive memory cell meets a programming criterion. In case that the magneto resistive memory cell does not meet the programming criterion, a second magnetic field, which is higher or lower than the first magnetic field, is applied to the magneto resistive memory cell. It is then determined whether the magneto resistive memory cell meets a programming criterion. The magnetic field is increased or decreased in case that the magneto resistive memory cell does not meet the programming criterion until the magneto resistive memory cell meets the programming criterion.

US Patent:

20080238468, Oct 2, 2008

Filed:

Mar 26, 2007

Appl. No.:

11/727291

Inventors:

Andre Sturm - Essex Junction VT, US
Thomas Vogelsang - Jericho VT, US
Marc Walter - Munchen, DE

Assignee:

Qimonda North America Corp. - Cary NC
Qimonda AG - Munich

International Classification:

G01R 31/02

US Classification:

324763

Abstract:

In a method or apparatus such as an integrated circuit (IC) chip including a plurality of circuits for executing a plurality of testmodes, a testmode entry code specifying one of the plurality of testmodes and one of an unrestricted private testmode category and a restricted public testmode category is received. Execution of only a public testmode of the plurality of testmodes is enabled when the testmode entry code specifies the restricted public testmode category. Execution of all of the plurality of testmodes is enabled when the testmode entry code specifies the unrestricted private testmode category.

US Patent:

20210376180, Dec 2, 2021

Filed:

May 29, 2020

Appl. No.:

16/887375

Inventors:

- Santa Clara CA, US
John J. ELLIS-MONAGHAN - Grand Isle VT, US
Mark D. LEVY - Williston VT, US
Vibhor JAIN - Williston VT, US
Andre STURM - Essex Junction VT, US

International Classification:

H01L 31/107
H01L 31/105
H01L 31/0312
H01L 31/028
H01L 31/036

Abstract:

The present disclosure relates to semiconductor structures and, more particularly, to photodiodes and/or PIN diode structures and methods of manufacture. The structure includes: at least one fin including substrate material, the at least one fin including sidewalls and a top surface; a trench on opposing sides of the at least one fin; a first semiconductor material lining the sidewalls and the top surface of the at least one fin, and a bottom surface of the trench; a photosensitive semiconductor material on the first semiconductor material and at least partially filling the trench; and a third semiconductor material on the photosensitive semiconductor material.