Amy W Tu

US Patent:

6737701, May 18, 2004

Filed:

Dec 5, 2002

Appl. No.:

10/313454

Inventors:

Amy C. Tu - San Jose CA
Jean Yee-Mei Yang - Sunnyvale CA
Yider Wu - Campbell CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 31119

US Classification:

257315, 257314

Abstract:

According to one exemplary embodiment, a structure comprises a first bit line and a second bit line. The structure further comprises a first memory cell situated over the first bit line, where the first memory cell comprises a first ONO stack segment, and where the first ONO stack segment is situated between the first bit line and a word line. The structure further comprises a second memory cell situated over the second bit line, where the second memory cell comprises a second ONO stack segment, where the second ONO stack segment is situated between the second bit line and the word line, and where the first ONO stack segment is separated from the second ONO stack segment by a gap. The first memory cell and the second memory cell may each be capable, for example, of storing two independent data bits.

US Patent:

6808948, Oct 26, 2004

Filed:

Dec 11, 2002

Appl. No.:

10/317797

Inventors:

Amy C. Tu - San Jose CA
Eugene W. Hill - Moss Beach CA
Samantha L. Doan - Mountain View CA
Mike Y. Kao - Saratoga CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2166

US Classification:

438 17, 438 18, 257 48

Abstract:

A method for evaluating the effect of crystalline originated pits (COPs) in a silicon substrate on semiconductor devices method locates a first test structure created on a COP on the substrate and a second test structure created on the substrate but not on a COP. The electrical properties of the first and second test structure are then examined and compared. If there is a difference in their electrical properties, then the COP would affect a structure similar to the test structures of a semiconductor device. In this manner, the effects of COPs on the yield for the substrate can be understood.

US Patent:

6828607, Dec 7, 2004

Filed:

Dec 9, 2002

Appl. No.:

10/315458

Inventors:

Mario M. Pelella - Mountain View CA
Amy C. Tu - San Jose CA
Richard K. Klein - Mountain View CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 29768

US Classification:

257250, 257239

Abstract:

A multiple independent bit Flash memory cell has a gate that includes a first oxide layer, a discontinuous nitride layer on the first oxide layer, a second oxide layer on the discontinuous nitride layer and the first oxide layer, and a polysilicon layer on the second oxide layer. The discontinuous nitride layer has regions residing at different portions of the layer. These portions are separated by the second oxide layer. Thus, with a smaller channel length, charge that otherwise would migrate from one region to the other and/or strongly influence its neighboring it is blocked/impeded by the second oxide layer. In this manner, the potential for charge sharing between the regions is reduced, and a higher density chip multiple independent bit Flash memory cells may be provided.

US Patent:

6858450, Feb 22, 2005

Filed:

Nov 5, 2002

Appl. No.:

10/288871

Inventors:

Samantha L. Doan - Mountain View CA, US
Amy C. Tu - San Jose CA, US
W. Eugene Hill - Moss Beach CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L031/26
H01L021/66

US Classification:

438 14, 438 78, 365 71

Abstract:

A method for in-line testing of a chip to include multiple independent bit Flash memory devices, includes the steps of: grounding every other polysilicon line on the chip to emulate the multiple independent bit Flash memory devices, where an oxide line reside between every two polysilicon lines; scanning the polysilicon lines with an electron beam; examining voltage contrasts between the polysilicon lines; and determining if there are consecutively grounded polysilicon lines based on the voltage contrasts. If consecutive polysilicon lines appear to be grounded, then this indicates that a bridge defect exists between two of the consecutively grounded polysilicon lines. With this method, bridge defects in multiple independent bit Flash memory devices are better detected, leading to improved yield and reliability of the devices.

US Patent:

7015135, Mar 21, 2006

Filed:

Dec 10, 2002

Appl. No.:

10/316569

Inventors:

Angela T. Hui - Fremont CA, US
Wenmei Li - Sunnyvale CA, US
Amy C. Tu - San Jose CA, US

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21/4763

US Classification:

438636, 438689, 438740

Abstract:

A method and system for providing at least one contact in a semiconductor device. The semiconductor device includes a substrate, an etch stop layer, an interlayer dielectric on the etch stop layer, an anti-reflective coating layer on the interlayer dielectric, and at least one feature below the etch stop layer. A resist mask having an aperture and residing on the anti-reflective coating layer is provided. The aperture is above an exposed portion of the anti-reflective coating layer. The method and system include etching the exposed anti-reflective coating layer and the underlying interlayer dielectric without etching through the etch stop layer, thereby providing a portion of at least one contact hole. The method and system also include removing the resist mask in situ, removing a portion of the etch stop layer exposed in the portion of the contact hole, and filling the contact hole with a conductive material.

US Patent:

6576548, Jun 10, 2003

Filed:

Feb 22, 2002

Appl. No.:

10/079861

Inventors:

Amy Tu - San Jose CA
Minh Van Ngo - Fremont CA
Austin Frenkel - Radebeul, DE
Robert J. Chiu - Mt. View CA
Jeff Erhardt - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 214763

US Classification:

438640, 438685, 438701, 438713

Abstract:

Reliable contacts/vias are formed by sputter etching to flare exposed edges of an opening formed in a dielectric layer, depositing a composite barrier layer and then filling the opening with tungsten at a low deposition rate. The resulting contact/via exhibits significantly reduced porosity and contact resistance. Embodiments include sputter etching to incline the edges of an opening formed in an oxide dielectric layer, e. g. , a silicon oxide derived from TEOS or BPSG, at an angle of about 83Â to about 86Â, depositing a thin layer of Ti, e. g. , at a thickness of about 250 to about 350 , depositing at least one layer of titanium nitride, e. g. , three layers of titanium nitride, at a total thickness of about 130 to about 170 , and then depositing tungsten at a deposition rate of about 1,900 to about 2,300 /min to fill the opening.