Amir W Habboosh

US Patent:

7580818, Aug 25, 2009

Filed:

Nov 1, 2005

Appl. No.:

11/265802

Inventors:

Piali De - Harvard MA, US
John A. Cogliandro - Dedham MA, US
John E. Rannenberg - N. Kingstown RI, US
Joe R. Wang - Boston MA, US
Amir W. Habboosh - Somerset MA, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G06F 9/455

US Classification:

703 6, 703 1, 705 1, 705 7

Abstract:

A method for mission profiling includes generating a human model including human activities and generating a system model including system functions. The method also includes generating an operational node model, including operational activities; and integrating the human model, the system model and the operational model to form an integrated mission model.

US Patent:

8174435, May 8, 2012

Filed:

Jun 1, 2010

Appl. No.:

12/791038

Inventors:

Amir W. Habboosh - Somerset MA, US
Nicholas F. Willis - E. Greenwich RI, US
Thomas E. Wood - Portsmouth RI, US

Assignee:

Raytheon Company - Waltham MA

International Classification:

G01S 13/00

US Classification:

342159, 342 91, 342205

Abstract:

Methods and apparatus to provide computing, using a processor, sea clutter threshold bias values as a function of range and azimuth, receiving a first shape corresponding to a first region of sea clutter about a radar, combining the sea clutter threshold bias values with the first shape to provide non-isotropic sensitivity time control (STC) for the radar, and outputting radar return for display with sea clutter suppressed in the first shape.

US Patent:

57869197, Jul 28, 1998

Filed:

Sep 5, 1996

Appl. No.:

8/706590

Inventors:

Amir W. Habboosh - Somerset MA
Robert J. Reid - Tiverton RI
Steven D. Jette - Exeter RI

Assignee:

The United States of America as represented by the Secretary of the Navy - Washington DC

International Classification:

H04J 300

US Classification:

359135

Abstract:

A multiplexing node is associated with each analog sensor of a line array. ach multiplexing node has an amplifier/filter section coupled to its associated analog sensor for amplifying and shaping a signal generated by the sensor. An A/D converter then samples the signal. A receiver is coupled to a previous one of the multiplexing nodes for receiving scrambled data and clock information in serial fashion from the previous node. A descrambler is coupled to the receiver to separate the data from the clock. A processor is coupled to the A/D converter and the descrambler. The processor time division multiplexes the data and clock from the previous node with the sampled signal from the A/D converter. The processor scrambles the so multiplexed data, clock and sampled signal. A transmitter is coupled to the processor to transmit the scrambled data, clock and sampled signal in serial fashion over a single data line.

US Patent:

20170026743, Jan 26, 2017

Filed:

Jul 24, 2015

Appl. No.:

14/808141

Inventors:

- Waltham MA, US
Amir W. Habboosh - Somerset MA, US
James Sturges - Tiverton RI, US

International Classification:

H04R 1/44

Abstract:

A shielded electronic array is provided and includes a main plate having opposing first and second major surfaces, first and second electronic devices disposed on respective first portions of the first and second major surfaces, respectively, a noise-shielding plate disposed on a second portion of the second major surface, an insulated eyelet, which is press-fittable into the main and noise-shielding plates and first and second wiring components. The first wiring component extends along a main plate plane from the second electronic device. The second wiring component extends from the first wiring component to the first electronic device and has an exposed first portion and a second portion extending through the insulated eyelet.