Alok Tripathi

US Patent:

6700455, Mar 2, 2004

Filed:

Aug 23, 2001

Appl. No.:

09/940147

Inventors:

Alok Tripathi - Beaverton OR
Dennis J. Miller - Sherwood OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03H 701

US Classification:

333 12, 333181, 439610, 439947

Abstract:

A method and apparatus for reducing electromagnetic emissions from a high-speed differential data connector is disclosed. The method and apparatus are as effective as a 360Â enclosure, while being easier and less expensive to manufacture and does not require a direct electrical connection between the Transistor-to-Transistor logic (TTL) or logic ground and the system chassis ground.

US Patent:

6710266, Mar 23, 2004

Filed:

Jul 26, 2002

Appl. No.:

10/205725

Inventors:

Jason A. Mix - Hillsboro OR
Yun Ling - Portland OR
Alok Tripathi - Beaverton OR
Kent E. Mallory - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 111

US Classification:

174261, 174255, 361788, 361799, 438 62

Abstract:

A technique to simultaneously reduce high-frequency insertion loss and cross-talk for a multi-layered add-in card is disclosed. The technique is based on selective removal of ground and power planes beneath the edge fingers. This selective removal of power and ground planes removes excess capacitance at the edge fingers, lowering the insertion loss at high frequencies, while maintaining an impedance match with an associated connector. Simultaneously, the leftover metallic ground/power plane provides electromagnetic shielding and thus reduces the cross-talk between the differential pairs. Optimum performance of the connector with minimized insertion loss and cross-talk can be obtained for high-speed analog and digital applications.

US Patent:

6801043, Oct 5, 2004

Filed:

Dec 20, 2002

Appl. No.:

10/326739

Inventors:

Alok Tripathi - Beaverton OR
Ken Drottar - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 2726

US Classification:

324642, 324647

Abstract:

According to some embodiments, time domain reflectometry based transmitter equalization is provided. For example, a reflection detector in a transmitter may detect a reflection signal associated with a calibration signal that was transmitted via an interconnect. The reflection detector may then provide filter information to a transmitting unit to facilitate a transmission of data to a remote receiver via the interconnect. According to some embodiments, the receiver adjusts a termination impedance before the calibration signal is transmitted.

US Patent:

7307492, Dec 11, 2007

Filed:

Nov 27, 2002

Appl. No.:

10/306418

Inventors:

Alok Tripathi - Beaverton OR, US
Dennis J. Miller - Sherwood OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01P 5/00
H01P 5/18
G06F 17/50

US Classification:

333111, 333113, 333115, 716 1

Abstract:

An apparatus that includes a first conducting strip having a narrowed width where the first conducting strip also acts as a first electrode for a first tapping capacitance. The first tapping capacitance has a second electrode that is: 1) parallel to the first conducting strip; and 2) closer to the first conducting strip than a second conducting strip. The second conducting strip is parallel to the first conducting strip and has a narrowed width where the second conducting strip also acts as a first electrode for a second tapping capacitance. The second tapping capacitance has a second electrode that is: 1) parallel to the second conducting strip; and 2) closer to the second conducting strip than the first conducting strip.

US Patent:

7391829, Jun 24, 2008

Filed:

Jul 2, 2003

Appl. No.:

10/612864

Inventors:

Alok Tripathi - Beaverton OR, US
Ken Drottar - Portland OR, US
Dave Dunning - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H04L 7/00

US Classification:

375345, 330254, 330278, 330299

Abstract:

In some embodiments, a frequency dependent gain circuit is coupled to an output of an amplifier. The gain circuit provides at least two ranges of frequency dependent gain characteristics in response to the output of the amplifier. A control circuit provides one of the at feast two gain values as an output. Other embodiments are described and claimed.

US Patent:

7402048, Jul 22, 2008

Filed:

Mar 30, 2006

Appl. No.:

11/393540

Inventors:

Pascal C. Meier - Sunnyvale CA, US
Michael W. Leddige - Beaverton OR, US
Mohiuddin Mazumder - San Jose CA, US
Mark Trobough - Olympia WA, US
Alok Tripathi - Beaverton OR, US
Ven R. Holalkere - Lakewood WA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01R 12/00

US Classification:

439 65

Abstract:

An apparatus includes a printed circuit board (PCB) and a first flexible conductive cable (“flex cable”) secured to the PCB. The apparatus also includes a daughter card having an end adjacent to the PCB and a second flex cable secured to the daughter card. The apparatus further includes a connector which provides an electrically conductive connection between the first flex cable and the second flex cable. The connector is positioned to sandwich a portion of the first flex cable between the connector and the PCB.

US Patent:

20050201454, Sep 15, 2005

Filed:

Mar 12, 2004

Appl. No.:

10/798557

Inventors:

Santanu Chaudhuri - Mountain View CA, US
James McCall - Beaverton OR, US
Konika Ganguly - Portland OR, US
Michael Gutzmann - Forest Grove OR, US
Sanjay Dabral - Palo Alto CA, US
Ken Drottar - Portland OR, US
Alok Tripathi - Beaverton OR, US
Kersi Vakil - Olympia WA, US

International Classification:

H03K005/159

US Classification:

375229000

Abstract:

A method to calibrate an equalizer for communicating signals over a data link between a transmitter and receiver includes measuring loss in the link and automatically determining a multi-tap equalization setting for the transmitter based on the measured loss. The multi-tap equalization setting may be determined using a look-up table, which stores a plurality of equalization settings for a respective number of link loss values. Once the equalization setting matching the measured link loss is found in the table, the equalizer can be optimally set to reduce or eliminate intersymbol and other types of interference.

US Patent:

20060291552, Dec 28, 2006

Filed:

Jun 22, 2005

Appl. No.:

11/159522

Inventors:

Evelina Yeung - San Jose CA, US
Sanjay Dabral - Palo Alto CA, US
James Jaussi - Hillsboro OR, US
Alok Tripathi - Beaverton OR, US

International Classification:

H03H 7/30
H04B 1/10

US Classification:

375233000, 375350000

Abstract:

In some embodiments, a circuit is provided that comprises a decision feedback equalizer to receive a bit stream signal. The equalizer comprises a summing circuit having a first input to receive a cursor bit sample from the bit stream, a second input to receive a first cursor bit signal, and an output to provide a cursor bit output signal corresponding to the cursor bit sample with at least some postcursor distortion removed therefrom. Other embodiments are disclosed and/or claimed herein.

Author:

Alok Tripathi

ISBN #:

8173200572

Author:

Alok Tripathi

ISBN #:

8175741554