Aljosa Vrancic

US Patent:

6640312, Oct 28, 2003

Filed:

Aug 1, 2000

Appl. No.:

09/629349

Inventors:

Andrew Thomson - Austin TX
David W. Madden - Austin TX
Glen Sescila - Pflugerville TX
Aljosa Vrancic - Austin TX

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 1100

US Classification:

714 5, 714 9, 714 43

Abstract:

A system and method for transferring data over a communications medium. A host is coupled to a device through a serial bus lacking error handling capabilities, such as an IEEE 1394 bus. The host may control the device by sending requests accessing its memory registers. The host generates a first request to the device to access a memory address location of the device, and which includes an address and status information indicating whether a prior request to the memory address location returned successfully. The device examines the status information to determine if it is a retry of a prior request, and if so, determines if the prior request completed successfully to the memory address location by comparing the address and data transfer size of the first request to those of the prior request. If identical, then the prior request completed successfully to the memory address location, and the request is ignored. Otherwise, the device retries the prior request.

US Patent:

6839777, Jan 4, 2005

Filed:

Sep 11, 2000

Appl. No.:

09/659914

Inventors:

Aljosa Vrancic - Austin TX, US
David W. Madden - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 300

US Classification:

710 52, 710 8, 710 22

Abstract:

A system and method for transferring data over a communications medium using data transfer links. A host computer may couple to a device through a serial bus. A buffer of contiguous virtual memory addresses may correspond to non-contiguous physical addresses, which may be stored in a linked list of transfer nodes, preserving the order of the original virtual buffer elements. Each transfer node specifies a data transfer between the host and device, and may be executed by the device DMA Controller. Each node may contain source and/or destination address information, size of the data to be transferred, and a link to the next node. The transfer nodes may be transferred to the device using a double-buffering scheme wherein the device executes the nodes from one half of the link buffer while the host computer transfers further nodes to be executed to the other half of the link buffer. The buffer halves may be switched back and forth between these two processes until all links are executed. To prevent overruns, safety and message links may be inserted into the transfer link list.

US Patent:

6985977, Jan 10, 2006

Filed:

Aug 30, 2002

Appl. No.:

10/231538

Inventors:

Aljosa Vrancic - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 3/00
G06F 13/28
G06F 3/06

US Classification:

710 59, 710 61, 710 53, 710 58, 710 60, 710 57, 710 5, 710 6, 710 22, 710 25, 710 28

Abstract:

System and method for transferring data to a device using double buffered data transfers. A host computer system couples to a data acquisition device. The device includes a first read buffer and a second read buffer for storing output data received from the host computer. The device reads first data from the computer and stores it in the first read buffer. The first data is transferred out from the first read buffer while the device reads second data from the computer and stores it in the second read buffer. The second data is transferred out from the second read buffer (after the transfer of the first data) while the device reads third data from the host computer and stores the third data in the first read buffer. Thus, the data acquisition device successively reads data into one read buffer concurrently with transferring data out from the other buffer, respectively.

US Patent:

7043565, May 9, 2006

Filed:

Aug 11, 2000

Appl. No.:

09/638051

Inventors:

David W. Madden - Austin TX, US
Aljosa Vrancic - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 15/16

US Classification:

709250, 709217, 709236, 709230, 709231, 710 6, 710 33, 710 35, 719310, 719316, 719321, 718100

Abstract:

A system and method for transferring data over an external transmission medium. A host computer is coupled to a device through a serial bus. A transfer object is configurable to encapsulate data transfer-related functionality, providing a generic interface for transmission of data over a variety of external transmission media and protocols. A user makes one or more transfer requests. Transfer objects corresponding to each request are built and linked together to form a sequential chain. The requests of the transfer objects are executed sequentially. If the current transfer object is the first in the chain, the request is executed on a current thread at passive level or higher, otherwise the request is executed on a system (kernel) thread at dispatch level. When a response to the request returns, control is returned to the current transfer object. The process is repeated until all transfer objects are processed.

US Patent:

7114091, Sep 26, 2006

Filed:

Mar 17, 2003

Appl. No.:

10/389784

Inventors:

Aljosa Vrancic - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 1/12

US Classification:

713400

Abstract:

A system may include a communication medium, a master node, and a slave node. The master node may send several sets of synchronization messages on the communication medium. Each set of synchronization messages includes several synchronization messages. The slave node may receive each set of synchronization messages and to select a synchronization message having an optimal delay from each set of synchronization messages. The slave node may calculate a correction for a slave clock included in the slave node in response to timing information associated with the synchronization message having the optimal delay in each set. The slave node may not calculate a correction for the slave clock in response to timing information associated with at least some of the synchronization messages in each set. The communication medium may convey at least one synchronization message within each of the sets with a minimum delay.

US Patent:

7559060, Jul 7, 2009

Filed:

Feb 23, 2004

Appl. No.:

10/784866

Inventors:

Darren R. Schmidt - Cedar Park TX, US
Aljosa Vrancic - Austin TX, US
Satish V. Kumar - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/46
G06F 9/44
G06F 11/00

US Classification:

718100, 718102, 718104, 717124, 717127, 717128, 717129, 717131, 714 2, 714 34, 714 48, 714 55

Abstract:

System and method for performing time-bounded execution of a program. A timed program execution process is initiated, and a timeout process is initiated. A timeout condition is configured in the timeout process at a first priority level, and a rollback state determined for the program. Execution of the program is initiated in the timed program execution process at a second priority level below the first priority level. During execution of the program, the timeout process determines if the timeout condition has occurred, and if so, the timeout process restores the execution of the program to the rollback state, and the timed program execution process resumes execution of the program from the rollback state with the timeout condition. The program exits in the timed program execution process in response to the timeout condition, and the timeout event disabled. The timeout process is terminated, and the timed program execution process is terminated.

US Patent:

7565609, Jul 21, 2009

Filed:

Aug 16, 2005

Appl. No.:

11/204779

Inventors:

Aljosa Vrancic - Austin TX, US
Jacob Kornerup - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 15/177
G06F 15/16

US Classification:

715734, 715736, 709248

Abstract:

A first graphical program executing on a first device may execute a first graphical code portion for a plurality of iteration. Various systems and methods for synchronizing the execution of the iterations of the first graphical code portion with graphical code portions executing iteratively in graphical programs on other devices are described. Various systems and methods for synchronizing the execution of the iterations of the first graphical code portion with operation of measurement devices or other devices are also described.

US Patent:

7574690, Aug 11, 2009

Filed:

Jul 16, 2004

Appl. No.:

10/892829

Inventors:

Biren Shah - Austin TX, US
Jacob Kornerup - Austin TX, US
Aljosa Vrancic - Austin TX, US
Jeffrey L. Kodosky - Austin TX, US
Michael L. Santori - Austin TX, US

Assignee:

National Instruments Corporation - Austin TX

International Classification:

G06F 9/44

US Classification:

717104, 700 83, 716 4, 715762, 710260

Abstract:

A system and method for creating a graphical program operable to execute a timed loop. A loop may be displayed in the graphical program and configured with timing information in response to user input. The timing information may include an execution period which specifies a desired period at which the loop should execute during execution of the graphical program. The timing information may also include information such as a timing source, offset, and priority. During execution of the graphical program, the execution period of the loop may control the rate at which the loop executes.