Alexander J Suess

US Patent:

7117466, Oct 3, 2006

Filed:

Sep 18, 2003

Appl. No.:

10/665273

Inventors:

Kerim Kalafala - Rhinebeck NY, US
Peihua Qi - Wappingers Falls NY, US
David J. Hathaway - Underhill Center VT, US
Alexander J. Suess - Hopewell Junction NY, US
Chandramouli Visweswariah - Croton-on-Hudson NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 4

Abstract:

A method of removing pessimism in static timing analysis is described. Delays are expressed as a function of discrete parameter settings allowing for both local and global variation to be taken in to account. Based on a specified target slack, each failing timing test is examined to determine a consistent set of parameter settings which produces the worst possible slack. The analysis is performed on a path basis. By considering only parameters which are in common to a particular data/clock path-pair, the number of process combinations that need to be explored is reduced when compared to analyzing all combinations of the global parameter settings. Further, if parameters are separable and linear, worst-case variable assignments for a particular clock/data path pair can be computed in linear time by independently assigning each parameter value. In addition, if available, the incremental delay change with respect to each physically realizable process variable may be used to project the worst-case variable assignment on a per-path basis without the need for performing explicit corner enumeration.

US Patent:

7398491, Jul 8, 2008

Filed:

May 26, 2006

Appl. No.:

11/420529

Inventors:

Gregory M. Schaeffer - Poughkeepsie NY, US
Alexander J. Suess - Hopewell Junction NY, US
David J. Hathaway - Underhill VT, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 4, 716 5, 716 6

Abstract:

A method for incrementally calculating the impact of coupling noise on the timing of an integrated circuit (IC) having a plurality of logic stages by performing an initial timing analysis on the IC to provide a first determination of the impact of coupling noise on the timing. One or more design changes to the IC are then performed. In response to the design change, the impact of the coupling noise to the timing is calculated on the logic stage where the change was made and on the logic stages downstream thereof. The results of the calculations are then inputted to a timing analysis tool to adjust the delay and slew of each logic stage where the design change was made and to the logic stages downstream thereof.

US Patent:

7650246, Jan 19, 2010

Filed:

Aug 31, 2005

Appl. No.:

11/162200

Inventors:

David J. Hathaway - Underhill VT, US
Alexander J. Suess - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G01R 15/00
G06F 19/00

US Classification:

702 57

Abstract:

A method and device for determining a delay of a gate driven by a driving gate with different ground or supply voltages. The method includes determining from the supply and ground voltages for the driven gate and its driving gate an adjusted supply voltage value, and applying the adjusted supply voltage value as a single voltage parameter to a pre-characterized delay model for the driven gate. The device is structured to perform the method.

US Patent:

7694254, Apr 6, 2010

Filed:

Jan 3, 2007

Appl. No.:

11/619349

Inventors:

James C. Gregerson - Hyde Park NY, US
Kerim Kalafala - Rhinebeck NY, US
Alexander Suess - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 6, 716 4, 716 5

Abstract:

Run-time reduction is achieved in timing performance of a logical design, such as a digital integrated circuit. A portion of the logical design that is expected to be stable with respect to timing performance, such as a clock tree, is identified. Timing sensitivities, including sensitivities to sources of variability, of the identified portion of the logical design are determined at a given instant. The timing sensitivities of the identified portion of the logical design are saved for re-use. The saved timing sensitivities are re-used throughout the timing analysis and in subsequent timing analyses.

US Patent:

7937604, May 3, 2011

Filed:

Apr 19, 2007

Appl. No.:

11/737289

Inventors:

Revanta Banerji - Beacon NY, US
David J. Hathaway - Underhill VT, US
Alex Rubin - Sunnyvale CA, US
Alexander J. Suess - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1/12
G06F 13/42
H04L 5/00
H04L 7/00

US Classification:

713401, 713400, 713500, 713502, 713503

Abstract:

A method for generating a skew schedule for a clock distribution network generates a schedule that accounts for both the timing requirements of the memory elements at the endpoints of the clock distribution network and the timing requirements of the gating signals that feed clock gates and other clock control elements within the clock distribution network. The method provides a total solution to the skew scheduling problem by way of a two-phase iterative process. The two phases of the process alternately keep track of the schedule generated by first taking the gating elements of the clock distribution network into account, followed by balancing any remaining skew that may exist on the memory elements of the same clock distribution network. Finally, the method describes a procedure to post-process the skew schedule to ensure that it can be implemented using a clock tree generation tool.

US Patent:

8495553, Jul 23, 2013

Filed:

Dec 9, 2011

Appl. No.:

13/315406

Inventors:

George Antony - Cochin, IN
Sridhar H. Rangarajan - Bangalore, IN
Alexander J. Suess - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716133, 716109

Abstract:

A computer-implemented method of determining threshold voltage levels within a macro of integrated circuit cells. In one embodiment, the method includes: referencing a library of the integrated circuit cells in the macro; estimating a leakage power and a dynamic power for a first integrated circuit cell in the macro; comparing the leakage power with the dynamic power; switching the first integrated circuit cell to a low threshold voltage level in response to determining the dynamic power is greater than the leakage power; and updating the library with a voltage level of the first integrated circuit cell.

US Patent:

6615395, Sep 2, 2003

Filed:

Dec 20, 1999

Appl. No.:

09/467208

Inventors:

David J. Hathaway - Underhill Center VT
Chandramouli V. Kashyap - Austin TX
Byron L. Krauter - Austin TX
Sharad Mehrotra - Austin TX
Alexander J. Suess - Hopewell Junction NY

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1750

US Classification:

716 6, 716 4, 716 5

Abstract:

A method for performing a static timing analysis on an integrated circuit chip or module taking into account the effect of wiring interconnection coupling is described. The wiring interactions are modeled as appropriate equivalent grounded capacitances, allowing traditional delay calculation methods to be applied. The method includes the steps of assigning a pessimistic value to the wiring coupling interaction between nets forming the integrated circuit chip; performing the static timing analysis using computed timing parameters which are a function of net capacitance, the net capacitance being based on the pessimistic value of the coupling interaction between the nets; updating the net capacitance of selected nets based on 1) an overlap between an arrival time window of each of the selected nets and a possible arrival time window of each of the other nets which are coupled to the each of selected nets, and 2) on the slew of each of the selected nets and the slew of each of the other nets which are coupled to the selected nets; and updating the static timing analysis based on the updated net capacitances of the selected nets.

US Patent:

20230090855, Mar 23, 2023

Filed:

Sep 20, 2021

Appl. No.:

17/479246

Inventors:

- Armonk NY, US
Basanth Jagannathan - Shrub Oak NY, US
Michael Hemsley Wood - Wilmington DE, US
Leon Sigal - Monsey NY, US
James Leland - Arlington TX, US
Alexander Joel Suess - Hopewell Junction NY, US
Benjamin Neil Trombley - Hopewell Junction NY, US
Paul G. Villarrubia - Austin TX, US

International Classification:

H02J 3/00

Abstract:

Embodiments for power generation include defining a power tile within a power distribution network having a grid of power rails, the power tile having logic gates, and applying an initial power grid pattern from a plurality of power grid patterns for the power tile such that initial power grid pattern relates to timing characteristics of the logic gates of the power tile. The power grid patterns each have a different number of connectors connecting one power rail to another power rail in the grid of power rails. A subsequent power grid pattern is selected from the power grid patterns for the power tile such that the subsequent power grid pattern meets a threshold condition for the timing characteristics of the logic gates of the power tile. The timing characteristics for the logic gates are determined based on a voltage drop associated with the subsequent power grid pattern.