Scott S. Roth - Austin TX William C. McFadden - Austin TX Alexander J. Pepe - Austin TX
Assignee:
Motorola Inc. - Schaumburg IL
International Classification:
H01L 27108 H01L 2976 H01L 29788
US Classification:
257316
Abstract:
A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
Method Of Forming A Transistor Having An Offset Channel Section
Scott S. Roth - Austin TX William C. McFadden - Austin TX Alexander J. Pepe - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 21265
US Classification:
437 41
Abstract:
The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
Method Of Making A Vertically Formed Neuron Transistor Having A Floating Gate And A Control Gate And A Method Of Formation
Scott S. Roth - Austin TX William C. McFadden - Austin TX Alexander J. Pepe - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 218247
US Classification:
437 43
Abstract:
A method for forming a vertical neuron MOSFET begins by providing a substrate (12). One or more conductive layers (24 and 28) are formed overlying the substrate (12). An opening (32) is formed through a portion of the conductive layers (24 and 28) to form one or more control electrodes from the conductive layers (24 and 28). A floating gate (36, and 38) is formed adjacent each of the control electrodes. A dielectric layer (34) is formed within the opening (32) and between the control electrodes and the floating gate (36, and 38) to provide for capacitive coupling between the control electrodes and the floating gate (36, and 38). The capacitive coupling may be altered for each control electrode via isotropic sidewall etching and other methods. By forming the neuron MOSFET in a vertical manner, a surface area of the neuron MOSFET is reduced when compared to known neuron MOSFET structures.
Scott S. Roth - Austin TX William C. McFadden - Austin TX Alexander J. Pepe - Austin TX
Assignee:
Motorola, Inc. - Schaumburg IL
International Classification:
H01L 2976 H01L 2994 H01L 31062 H01L 31113
US Classification:
257393
Abstract:
The present invention includes a transistor having a channel region with a first and second section, wherein the sections have lengths that generally perpendicular to one another. The prevent invention also includes the transistor in an SRAM cell and processes for forming the transistor and the SRAM cell. In the embodiments that are described, the first section has a length that is generally vertical and the second section has a length that is generally extends in a lateral direction. The first section may be an undoped or lightly doped portion of a silicon plug. The plug may be formed including an etching or polishing step.
Name / Title
Company / Classification
Phones & Addresses
Alexander John Pepe Director, Manager
AKP REAL ESTATE HOLDINGS, LLC
1500 Palisades Pointe Ln, Austin, TX 78738
Alexander J Pepe Governing, Governing Person
AJP CONSULTING, LLC Business Consulting Services
1500 Palisades Pointe Ln, Austin, TX 78738
Alexander Pepe Svp Global Front-end Operations And Procurement