Alan W Fulton

US Patent:

40765563, Feb 28, 1978

Filed:

Jun 1, 1976

Appl. No.:

5/691594

Inventors:

Jorge Agraz-Guerena - Puebla, MX
Alan William Fulton - Batavia IL

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

H01L 21265
H01L 2702

US Classification:

148 15

Abstract:

An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

US Patent:

41997751, Apr 22, 1980

Filed:

Sep 3, 1974

Appl. No.:

5/502674

Inventors:

Jorge Agraz-Guerena - Puebla, MX
Alan W. Fulton - Batavia IL

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

H01L 2710

US Classification:

357 46

Abstract:

An integrated transistor circuit arrangement provides a multicollector transistor with Schottky diodes and ohmic connections selectively formed at the collector terminals. In the illustrative example, a vertical transistor is formed in an N-type epitaxial layer overlying an N+ substrate. A through-extending region of P+ material encircles the region of the epitaxial layer in which the vertical transistor is formed. The base of the vertical transistor is formed by the implanting of P-type impurity in a location spaced apart from the surfaces of the epitaxial layer. The resulting base has a symmetrical profile relative to the faces of the epitaxial layer. Therefore, the transistor may be operated with the collector at the surface without penalty of electrical operation. In the illustrative example, a PNP lateral transistor is utilized as a current source for the vertical transistor.

US Patent:

41258533, Nov 14, 1978

Filed:

Mar 28, 1977

Appl. No.:

5/781788

Inventors:

Alan W. Fulton - Batavia IL
William J. Ooms - Schaumburg IL
Ray A. Reed - Bolingbrook IL

Assignee:

Bell Telephone Laboratories, Incorporated - Murray Hill NJ

International Classification:

H01L 2972

US Classification:

357 36

Abstract:

Several embodiments of isolated lateral transistors are shown. The emitter and collector electrodes of each embodiment are formed in the same processing step as the region which isolates the transistor from other structures. Consequently, the emitter and collector electrodes are each relatively heavily doped and extend to an underlying buried layer over which the transistor is formed. The heavy doping and the deep penetration of the collector and emitter diffusions tend to increase transistor efficiency; and since the emitter and collector electrodes are formed in the same processing step as the isolation diffusion, there is a reduction in processing complexity.