Alan D Baker

US Patent:

59374241, Aug 10, 1999

Filed:

Feb 27, 1997

Appl. No.:

8/807385

Inventors:

David A. Leak - Rancho Cordova CA
Fasil G. Bekele - San Francisco CA
Thomas C. Price - Fair Oaks CA
Alan E. Baker - Granite Bay CA
Charles W. Brown - Folsom CA
Peter K. Hazen - Auburn CA
Vishram Prakash Dalvi - Fair Oaks CA
Rodney R. Rozman - Placerville CA
Christopher John Haid - Folsom CA
Jerry Kreifels - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200
G11C 1134

US Classification:

711103

Abstract:

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register, and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

US Patent:

53011511, Apr 5, 1994

Filed:

Jun 15, 1993

Appl. No.:

8/077326

Inventors:

Steve Wells - Citrus Heights CA
Alan Baker - Fair Oaks CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

30518909

Abstract:

Circuitry for locking out a first signal generated from a first power supply while the first power supply is at or below a first voltage level is described for a non-volatile semiconductor memory. The circuitry includes a first P-type transistor P1 having a gate, a drain, and a source. The source of P1 is coupled to a second power supply, the drain of P1 is coupled to a first node and the gate of P1 is coupled to a second node. The second node provides an output signal representative of the first control signal. The circuitry also includes a first N-type transistor N1, having a gate, a drain, and a source. The drain of N1 is coupled to the first node, the source of N1 is coupled to a third, and the gate of N1 is coupled to the first control signal and to a fourth node. Included is a second N-type transistor N2, having a drain, a source and a gate. The gate of N2 is coupled a sixth node.

US Patent:

49758837, Dec 4, 1990

Filed:

Mar 29, 1990

Appl. No.:

7/501140

Inventors:

Alan E. Baker - Fair Oaks CA
Richard J. Durante - Citrus Heights CA
Owen W. Jungroth - Sonora CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 700

US Classification:

365226

Abstract:

A circuit is disclosed for preventing the erasing and programming of a nonvolatile memory device during power up and power down transitions. A power supply generator incorporating an n-channel device and a w-channel device in a wired-or configuration is coupled to a programming voltage Vpp and to a circuit voltage Vcc, and generates a node voltage Vpwr which is the greater of Vpp-Vtn and Vcc-Vtw. Vtn is the gate threshold voltage of the n-channel device, while Vtw is the gate threshold voltage of the w-channel device. The node voltage Vpwr is coupled to a reference voltage generator which provides a reference voltage, a protecting voltage, and a biasing voltage for a Vcc comparator and a Vpp comparator. The Vcc comparator and the Vpp comparator compare Vref with the output of a Vcc divide-by-two circuit and a Vpp divide-by-five cirucit, respectively. Thus, during the power up transition of the nonvolatile memory device where over-erasing may damage the memory array, the circuit forces the nonvolatile memory device into read mode, ensuring that no damaging voltage reaches the memory array.

US Patent:

61483605, Nov 14, 2000

Filed:

Sep 20, 1996

Appl. No.:

8/718216

Inventors:

David A. Leak - Rancho Cordova CA
Fasil G. Bekele - San Francisco CA
Thomas C. Price - Fair Oaks CA
Alan E. Baker - Granite Bay CA
Charles W. Brown - Folsom CA
Peter K. Hazen - Auburn CA
Vishram Prakash Dalvi - Fair Oaks CA
Rodney R. Rozman - Placerville CA
Christopher John Haid - Folsom CA
Jerry Kreifels - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1324

US Classification:

710260

Abstract:

A method and apparatus suspend a program operation in a nonvolatile writeable memory. The nonvolatile writeable memory includes a memory array, a command register and memory array control circuitry. The command register decodes a program suspend command and provides a suspend signal as an output. The memory array control circuitry is coupled to receive the suspend signal from the command register. The memory array control circuitry performs a program operation in which data is written to the memory array. The memory array control circuitry suspends the program operation upon receiving the suspend signal.

US Patent:

52220460, Jun 22, 1993

Filed:

Oct 19, 1990

Appl. No.:

7/601012

Inventors:

Jerry A. Kreifels - Citrus Heights CA
Alan Baker - Fair Oaks CA
George Hoekstra - Santa Clara CA
Virgil N. Kynett - El Dorado Hills CA
Steven Wells - Orangevale CA
Mark Winston - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 800

US Classification:

36523006

Abstract:

A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.

US Patent:

50539906, Oct 1, 1991

Filed:

Feb 17, 1988

Appl. No.:

7/157361

Inventors:

Jerry A. Kreifels - Citrus Heights CA
Alan Baker - Fair Oaks CA
George Hoekstra - Santa Clara CA
Virgil N. Kynett - El Dorado Hills CA
Steven Wells - Orangevale CA
Mark Winston - El Dorado Hills CA

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G11C 11407

US Classification:

364900

Abstract:

A semiconductor flash EPROM/EEPROM device which includes a command port for receiving instruction on a data line and providing control signals to a memory for providing program and erase functions, a method to program and erase the memory. A program sequence is comprised of setting up a program command during a first write cycle, preforming a second write cycle to load address to address register and data to to a data register, programming during a program cycle and writing a program verify command during a third write cycle to verify the programmed data during a read cycle. An erase sequence is comprised of writing a setup erase command during a first write cycle, an erase command during a second write cycle providing the erasure during an erase cycle, writing the erase verify command during a third write cycle which also addresses the address of the memory and providing erase verification during a read cycle. Both the erase and program cycles provide for measured incremental erasing and programming.

Author:

Alan Baker

ISBN #:

0091362903

Author:

Alan Baker

ISBN #:

0233968954

Author:

Alan Baker

ISBN #:

0233984380

Author:

Alan Baker

ISBN #:

0306811855

Author:

Alan Baker

ISBN #:

0312109024