Salman Abida Akram

US Patent:

6335230, Jan 1, 2002

Filed:

Jan 4, 2000

Appl. No.:

09/477203

Inventors:

Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2100

US Classification:

438149, 438151, 438154, 438197, 438353, 438355, 438405, 438412

Abstract:

A method of forming a MOS device using doped and activated n-type and p-type polysilicon layers wherein a first doped and activated polysilicon layer (either n-type and p-type) is patterned on a substrate. An isolation material layer is formed abutting the first doped and activated polysilicon layer in the corners formed at the junction between the first doped and activated polysilicon layer and the substrate. A second doped and activated polysilicon layer (either n-type or p-type) is applied over the first doped and activated polysilicon layer and the isolation material layer. The second doped and activated polysilicon layer is planarized to the height of the first doped and activated polysilicon layer. The first and second doped and activated polysilicon layers are etched to substantially bifurcate the first and second doped and activated polysilicon layers. Further processing steps known in the art are utilized to complete the MOS device.

US Patent:

6337575, Jan 8, 2002

Filed:

Dec 23, 1998

Appl. No.:

09/221216

Inventors:

Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 1073

US Classification:

324760, 324757

Abstract:

A method of testing integrated circuitry includes providing a substrate comprising integrated circuitry to be tested. The circuitry substrate to be tested has a plurality of exposed conductors in electrical connection with the integrated circuitry. In one implementation, at least some of the exposed conductors of the circuitry substrate are heated to a temperature greater than 125Â C. and within at least 50% in degrees centigrade of and below the melting temperature of the exposed conductors of the circuitry substrate. In one implementation, such are heated to a temperature below their melting temperature yet effective to soften said at least some of the exposed conductors to a point enabling their deformation upon application of less than or equal to 30 grams of pressure per exposed conductor. The circuitry substrate is engaged with a tester substrate. The tester substrate has a plurality of exposed conductors at least some of which are positioned to align with exposed conductors of the circuitry substrate.

US Patent:

6337577, Jan 8, 2002

Filed:

Feb 4, 1999

Appl. No.:

09/244373

Inventors:

C. Patrick Doherty - Boise ID
Jorge L. deVarona - Boise ID
Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3126

US Classification:

324765, 324754, 324755

Abstract:

An interconnect, a test system, and a test method for testing bumped semiconductor components, such as dice and packages, contained on substrates, such as wafers or panels, are provided. The test system includes the interconnect, a tester for generating test signals, and a wafer prober for placing the components and interconnect in physical contact. The interconnect includes interconnect contacts, such as conductive pockets, for electrically engaging bumped component contacts on the components. The interconnect also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the interconnect contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple components in parallel. Reading of the test signals from the components can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each component, and permits defective components to be electrically disconnected.

US Patent:

6338880, Jan 15, 2002

Filed:

Sep 4, 1998

Appl. No.:

09/148373

Inventors:

Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

C23C 1634

US Classification:

427575, 427576, 427255394, 438681, 438685

Abstract:

A process for depositing titanium nitride films containing less than 5% carbon impurities and less than 10% oxygen impurities by weight via chemical vapor deposition is disclosed. Sheet resistance of the deposited films is generally be within a range of about 1 to 10 ohms per square. The deposition process takes place in a deposition chamber that has been evacuated to less than atmospheric pressure and utilizes the organometallic compound tertiary-butyltris-dimethylamido-titanium and a nitrogen source as precursors. The deposition temperature, which is dependent on the nitrogen source, is within a range of 350Â C. to 700Â C. The low end of the temperature range utilizes nitrogen-containing gases such as diatomic nitrogen, ammonia, hydrazine, amides and amines which have been converted to a plasma. The higher end of the temperature range relies on thermal decomposition of the nitrogen source for the production of reaction-sustaining radicals. In such a case, the use of diatomic nitrogen gas is precluded because of its high dissociation temperature.

US Patent:

6339210, Jan 15, 2002

Filed:

Jul 20, 2000

Appl. No.:

09/620182

Inventors:

David R. Hembree - Boise ID
Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H05B 100

US Classification:

219209, 174 521, 257704

Abstract:

An inventive system for attaching a die to the die pad of a lead frame incorporating a resistive heating circuit into the die pad which heats up to cure an epoxy adhesive between the die and the pad and thereby attach the die to the pad. The heating circuit also heats up to loosen the adhesive so the die can be detached from the pad for rework. The resistive heating circuit is also incorporated into a Thin Small Outline Package (TSOP) between the TSOPs base and die cover. When the heating circuit in the TSOP heats up, it either cures an epoxy adhesive between the base and die cover to attach the die cover to the base, or it loosens the adhesive to detach the die cover from the base so a die inside the TSOP can be reworked. Thus, the inventive system eliminates the need for cumbersome curing ovens and, at the same time, provides a previously unavailable ability to rework certain semiconductor dice after they are packaged.

US Patent:

6339256, Jan 15, 2002

Filed:

Jan 5, 1999

Appl. No.:

09/225278

Inventors:

Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2352

US Classification:

257691, 257680, 257700, 257720

Abstract:

An inventive printed circuit board for chip-on-board applications has a ground plane that is externally exposed through apertures in any overlying layers in the board so the backside surface of a bare integrated circuit die can be directly attached to the ground plane using a silver-filled epoxy. As a result, heat is conducted away from the die through the ground plane. Also, a substrate bias voltage can be supplied to the backside surface of the die through the ground plane to eliminate the need for an internal substrate bias to the die, and to eliminate the need for a substrate bias voltage bond pad on the front-side surface of the die.

US Patent:

6342724, Jan 29, 2002

Filed:

Sep 25, 2000

Appl. No.:

09/668853

Inventors:

James M. Wark - Boise ID
Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2900

US Classification:

257532, 257924, 438108, 438393, 438396

Abstract:

A semiconductor device including a thin capacitor coupon mounted to the backside of a semiconductor die. When mounted active surface up on a carrier substrate of a multi-chip module, the coupon is secured between the backside of the die and the substrate. When flip-chip connections or direct chip attach are employed between the die and substrate, the coupon is secured to the backside of the die. The coupons may be preformed, or formed on the die in a wafer-scale fabrication process prior to singulation of the dice.

US Patent:

6349396, Feb 19, 2002

Filed:

Dec 21, 2000

Appl. No.:

09/745834

Inventors:

Salman Akram - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G01R 3128

US Classification:

714724, 714734, 324765

Abstract:

A burn-in testing system for evaluating a circuit under test, the system including a burn-in board having a plurality of receptacles, at least one of which being sized to receive the circuit under test, test interface circuitry supported by the board and coupled to the receptacles, the test interface circuitry including a transmitter and receiver; power conductors supported by the board, coupled to the receptacles and configured to be connected to a power supply to power the circuit under test during burn-in testing, control and data signal conductors, a burn-in oven having a compartment selectively receiving the burn-in board and being configured to apply heat within the compartment, and an interrogator unit supported by the burn-in oven, the interrogator unit being configured to send commands to the test interface circuitry to exercise the circuit under test optically or via radio communication and to receive responses to the commands optically or via radio communication. A method for testing an integrated circuit having operational circuitry formed thereon, optically and via radio frequency.