Adam P Donlin from San Jose, CA, age 51

Resumes

Equipment Manager

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Work:

Sju Men’s Hockey
Equipment Manager

Us Patents

Method And Apparatus For Configuring A Programmable Logic Device Using A Master Jtag Port
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US Patent:

6948147, Sep 20, 2005
Filed:

Apr 3, 2003
Appl. No.:

10/407327
Inventors:

Bernard J. New - Carmel Valley CA, US
Adam P. Donlin - Los Gatos CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F017/50
US Classification:

716 16, 716 17
Abstract:

Method and apparatus for configuring a programmable logic device using configuration data stored in an external memory is described. In an example, a boundary scan port includes a data input terminal and a data output terminal. An instruction-set processor includes a first interface coupled to the boundary scan port and a second interface coupled to a configuration memory within the programmable logic device. The data output terminal of the boundary scan port is coupled to provide instruction data to the external memory and the data input terminal is coupled to receive configuration data from the external memory in response to the instruction data. The instruction-set processor is configured to provide configuration data to the configuration memory.

Method And Apparatus For Communication Within A Programmable Logic Device Using Serial Transceivers
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US Patent:

7062586, Jun 13, 2006
Filed:

Apr 21, 2003
Appl. No.:

10/420418
Inventors:

Adam P. Donlin - Los Gatos CA, US
Bernard J. New - Carmel Valley CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 13/38
H03K 19/177
US Classification:

710305, 710317, 716 12, 326 39
Abstract:

Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.

Physically-Enforced Time-Limited Cores And Method Of Operation
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US Patent:

7183799, Feb 27, 2007
Filed:

Feb 25, 2005
Appl. No.:

11/067423
Inventors:

Adam P. Donlin - Los Gatos CA, US
Stephen M. Trimberger - San Jose CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

H03K 19/173
US Classification:

326 38, 326 8
Abstract:

A programmable logic device may comprise a metric circuit operable to repeatedly perform a function and emit a first signal dependent upon its advancement into the function. A comparator may compare the first signal from the metric circuit to a predetermined reference signal. A controller may then selectively disable a portion of the programmable logic device dependent upon the results of the comparison. In a particular case, the weakened circuit may be a counter that repeatedly advances its count with a rate dependent upon an aging characteristic of a vulnerable element.

Programmably Configurable Logic-Based Macro
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US Patent:

7337422, Feb 26, 2008
Filed:

May 10, 2005
Appl. No.:

11/126130
Inventors:

Tobias J. Becker - Bergisch Gladbach, DE
Adam P. Donlin - Los Gatos CA, US
Brandon J. Blodget - Santa Clara CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 17/50
US Classification:

716 16, 716 17, 716 18
Abstract:

A programmably configurable logic-based macro is described. Portions of configuration logic blocks for interconnectivity are assigned. The portions are configured as respective shift registers. Interconnects are routed between design static locations associated to provide interconnectivity between the portions. The portions assigned and routed are saved as a macro file. Inputs and outputs of the macro file are defined in a hardware description language. The hardware description language definition of the inputs and the outputs of the macro file are synthesized to provide a bitstream for programming programmably configurable logic associated with the portions. A shift register-to-shift register module interface boundary is created within an array of the programmably configurable logic.

System And Method For Accessing Signals Of A User Design In A Programmable Logic Device
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US Patent:

7353474, Apr 1, 2008
Filed:

Apr 18, 2006
Appl. No.:

11/405903
Inventors:

Adam P. Donlin - Los Gatos CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 17/50
G06F 15/177
G06F 9/00
G06F 11/263
G06F 11/267
G01R 13/28
US Classification:

716 4, 716 16, 716 18, 703 16, 713 2, 713100, 714 32, 714 39, 714732, 714733
Abstract:

Access to a signals of a user design in a programmable logic device (PLD) is provided without a compilation delay following selection of the signals. The system may include a generator, a compiler, a selector, the PLD, and a monitor. The generator selects sets of signals of the user design, and for each set of signals, generates a respective supplement of a subset of the user design supplementing the subset with a logic analyzer coupled to the set of signals. The compiler generates a respective configuration for each supplement. The selector selects a configuration or multiple configurations responsive to the specified set of signals and the sets of signals. The PLD implements the user design after the PLD is programmed with the selected configuration or configurations. The monitor accesses the specified set of signals in the PLD via the logic analyzer corresponding to each of the selected configuration or configurations.

Soft Injection Rate Control For Buses Or Network-On-Chip With Tdma Capability
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US Patent:

7380035, May 27, 2008
Filed:

Mar 24, 2005
Appl. No.:

11/090118
Inventors:

Adam P. Donlin - Los Gatos CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 13/368
US Classification:

710123, 710116
Abstract:

A programmable logic device, in accordance with an embodiment of the present invention, may comprise a bus and a plurality of programmable masters configurable to interface the bus. A first portion of a memory may include configuration data operable to configure masters of the plurality, while a second portion of the memory may include access patterns to control when the different masters of the plurality may access the bus. An injection rate controller may control when a given master is to send data on the bus based on the access pattern associated with the master. A master controller may be operable to write the access patterns for the masters to the second portion of the configuration memory.

Virtual File System Interface To Configuration Data Of A Pld
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US Patent:

7480789, Jan 20, 2009
Filed:

Mar 29, 2004
Appl. No.:

10/812643
Inventors:

Adam P. Donlin - Los Gatos CA, US
Patrick Lysaght - Los Gatos CA, US
Brandon J. Blodget - Santa Clara CA, US
Assignee:

Xilinx, Inc. - San Jose CA
International Classification:

G06F 9/00
G06F 9/24
US Classification:

713 1, 713 2, 713100
Abstract:

Methods and apparatus are described for providing access to data in a programmable logic device (PLD). A hierarchy of directories and files are maintained in a virtual file system, which is registered with an operating system. The directories and files are associated with resources of a PLD. In response to program calls to file system routines that reference files associated with resources of the PLD, the virtual file system is invoked, and the virtual file system accesses state information in resources of the PLD.

Method And Apparatus For Communication Within A Programmable Device Using Serial Transceivers
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US Patent:

7546408, Jun 9, 2009
Filed:

Apr 18, 2006
Appl. No.:

11/405962
Inventors:

Adam P. Donlin - Los Gatos CA, US
Bernard J. New - Carmel Valley CA, US
Assignee:

XILINX, Inc. - San Jose CA
International Classification:

G06F 13/38
H03K 19/177
US Classification:

710305, 710317, 716 16, 326 39
Abstract:

Method and apparatus for communication within a programmable logic device using serial transceivers is described. In an example, an integrated circuit includes a first module and a second module. The first module and the second module each include a transceiver coupled to a serial/parallel interface, with each transceiver configured with at least one signal conductor for serial communication between the first module and the second module. The first module and the second module are configured to communicate with one another asynchronously. Each transceiver is configured to communicate with its respective serial/parallel interface in a synchronous time domain.