Aaron A Budrevich

US Patent:

7759241, Jul 20, 2010

Filed:

Sep 15, 2006

Appl. No.:

11/521941

Inventors:

Aaron A. Budrevich - Portland OR, US
Adrien R. Lavoie - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/4763

US Classification:

438618, 438622, 257E21627

Abstract:

A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and method to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

US Patent:

7790536, Sep 7, 2010

Filed:

Aug 10, 2009

Appl. No.:

12/538828

Inventors:

Mantu K. Hudait - Portland OR, US
Aaron A. Budrevich - Portland OR, US
Dmitri Loubychev - Bethlehem PA, US
Jack T. Kavalieros - Portland OR, US
Suman Datta - Beaverton OR, US
Joel M. Fastenau - Bethlehem PA, US
Amy W. K. Liu - Mountain View CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/337

US Classification:

438191, 438 93, 438 94, 267E21398, 267E21407

Abstract:

A device grade III-V quantum well structure and method of manufacture is described. Embodiments of the present invention enable III-V InSb quantum well device layers with defect densities below 1×10cmto be formed. In an embodiment of the present invention, a delta doped layer is disposed on a dopant segregation barrier in order to confine delta dopant within the delta doped layer and suppress delta dopant surface segregation.

US Patent:

7842983, Nov 30, 2010

Filed:

Jun 26, 2008

Appl. No.:

12/215250

Inventors:

Ashutosh Ashutosh - Hillsboro OR, US
Huicheng Chang - Portland OR, US
Adrien R. Lavoie - Portland OR, US
Aaron A. Budrevich - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 29/76

US Classification:

257288, 257327, 257E29255, 438197, 438217, 438289

Abstract:

A device is annealed in a deuterium atmosphere. Deuterium penetrates the device to a boundary, which is passivated by the deuterium.

US Patent:

8222746, Jul 17, 2012

Filed:

Sep 28, 2006

Appl. No.:

11/540386

Inventors:

Adrien R. Lavoie - Beaverton OR, US
Juan E. Dominguez - Hillsboro OR, US
Aaron A. Budrevich - Portland OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/48

US Classification:

257774, 438686

Abstract:

Noble metal barrier layers are disclosed. In one aspect, an apparatus may include a substrate, a dielectric layer over the substrate, and an interconnect structure within the dielectric layer. The interconnect structure may have a bulk metal and a barrier layer. The barrier layer may be disposed between the bulk metal and the dielectric layer. The barrier layer may include one or more metals selected from iridium, platinum, palladium, rhodium, osmium, gold, silver, rhenium, ruthenium, tungsten, and nickel.

US Patent:

8258627, Sep 4, 2012

Filed:

Jun 18, 2010

Appl. No.:

12/818948

Inventors:

Aaron A. Budrevich - Portland OR, US
Adrien R. Lavoie - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 23/532

US Classification:

257751, 257762, 257E23161, 257E23157

Abstract:

A plurality of metal interconnects incorporating a Group II element alloy for protecting the metal interconnects and methods to form and incorporate the Group II element alloy are described. In one embodiment, a Group II element alloy is used as a seed layer, or a portion thereof, which decreases the line resistance and increases the mechanical strength of a metal interconnect. In another embodiment, a Group II element alloy is used to form a barrier layer, which, in addition to decreasing the line resistance and increasing the mechanical integrity, also increases the chemical integrity of a metal interconnect.

US Patent:

8394694, Mar 12, 2013

Filed:

Mar 19, 2007

Appl. No.:

11/725521

Inventors:

Adrien R. Lavoie - Beaverton OR, US
Aaron A. Budrevich - Portland OR, US
Ashutosh Ashutosh - Hillsboro OR, US
Huicheng Chang - Beaverton OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 21/8238
H01L 21/02

US Classification:

438216, 257410, 257E21423, 257E29309

Abstract:

A method for improving the reliability of a high-k gate dielectric layer comprises incorporating a noble metal into a transistor gate stack that contains the high-k gate dielectric layer and annealing the transistor gate stack in a molecular hydrogen or deuterium containing atmosphere. The annealing process drives at least a portion of the molecular hydrogen or deuterium toward the high-k gate dielectric layer. When the molecular hydrogen or deuterium contacts the noble metal, it is converted into atomic hydrogen or deuterium that is able to treat the high-k gate dielectric layer and improve its reliability.

US Patent:

20070063279, Mar 22, 2007

Filed:

Sep 16, 2005

Appl. No.:

11/231002

Inventors:

Peter Tolchinsky - Beaverton OR, US
Mohamad Shaheen - Portland OR, US
Martin Giles - Portland OR, US
Irwin Yablok - Portland OR, US
Aaron Budrevich - Portland OR, US

International Classification:

H01L 27/12
H01L 27/01
H01L 31/0392
H01L 21/84
H01L 21/00

US Classification:

257347000, 438149000

Abstract:

A method of forming a silicon-on-insulator wafer begins by providing a silicon wafer having a first surface. An ion implantation process is then used to implant oxygen within the silicon wafer to form an oxygen layer that is buried within the silicon wafer, thereby forming a silicon device layer that remains substantially free of oxygen between the oxygen layer and the first surface. An annealing process is then used to diffuse nitrogen into the silicon wafer, wherein the nitrogen diffuses into the silicon device layer and the oxygen layer. Finally, a second annealing process is used to form a silicon dioxide layer and a silicon oxynitride layer, wherein the second annealing process causes the implanted oxygen to react with the silicon to form the silicon dioxide layer and causes the diffused nitrogen to migrate and react with the silicon and the implanted oxygen to form the silicon oxynitride layer.

US Patent:

20070207611, Sep 6, 2007

Filed:

Mar 3, 2006

Appl. No.:

11/367160

Inventors:

Adrien Lavoie - Beaverton OR, US
Juan Dominguez - Hillsboro OR, US
Aaron Budrevich - Portland OR, US

International Classification:

H01L 21/44

US Classification:

438687000

Abstract:

A copper interconnect oh a semiconductor substrate comprises a dielectric layer having a trench, a noble metal layer on the dielectric layer within the trench, and a copper interconnect on the noble metal layer. The noble metal layer has a thickness that is between 3 Å and 100 Å and a density that is greater than or equal to 5 g/cm. The copper interconnect may be formed by etching a trench into the dielectric layer, pulsing a noble metal containing precursor proximate to the semiconductor substrate, and pulsing a reactive gas proximate to the semiconductor substrate, wherein the reactive gas reacts with the precursor to form a noble metal layer on the dielectric layer. A copper layer may then be deposited atop the noble metal layer and planarized. The noble metal layer functions as a barrier to copper diffusion and provides a surface upon which the copper metal can nucleate.